Bug 831 - Fix pseudo-code parser to correctly ignore html comments
Summary: Fix pseudo-code parser to correctly ignore html comments
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- major
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks:
 
Reported: 2022-05-03 10:50 BST by Jacob Lifshay
Modified: 2022-05-03 11:09 BST (History)
1 user (show)

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Description Jacob Lifshay 2022-05-03 10:50:30 BST
Fix parser to work when the linked-below commit is reverted. The commit should not be reverted until the parser is fixed, otherwise people can't work on the pseudo-code meanwhile because it errors out.

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=4e181c8e868230e930292df33f9985c3bb78e30c
Comment 1 Luke Kenneth Casson Leighton 2022-05-03 10:52:18 BST
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=2b1d3614362d4f1a18d28d8d324b7f275a62f5bf

should be sorted.
Comment 2 Jacob Lifshay 2022-05-03 11:09:47 BST
(In reply to Luke Kenneth Casson Leighton from comment #1)
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=2b1d3614362d4f1a18d28d8d324b7f275a62f5bf
> 
> should be sorted.

still broke:
page svfixedarith madded /home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/isa/svfixedarith.py madded
<!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
<!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
<!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
prod[0:127] <- (RA) * (RB)
sum[0:127] <- EXTZ(RC) + prod
RT <- sum[64:127]
RS <- sum[0:63]

form VA
Fields(RA=(sig VA_RA), RB=(sig VA_RB), RC=(sig VA_RC), RT=(sig VA_RT), SHB=(sig VA_SHB), VRA=(sig VA_VRA), VRB=(sig VA_VRB), VRC=(sig VA_VRC), VRT=(sig VA_VRT), XO=(sig VA_XO))
Fields(RA=(sig VA_RA), RB=(sig VA_RB), RC=(sig VA_RC), RT=(sig VA_RT), SHB=(sig VA_SHB), VRA=(sig VA_VRA), VRB=(sig VA_VRB), VRC=(sig VA_VRC), VRT=(sig VA_VRT), XO=(sig VA_XO))
Traceback (most recent call last):
  File "/home/jacob/.virtualenvs/libre-riscv-venv/bin/pywriter", line 11, in <module>
    load_entry_point('libresoc-openpower-isa', 'console_scripts', 'pywriter')()
  File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/pseudo/pywriter.py", line 171, in pywriter
    isa.write_pysource(source)
  File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/pseudo/pywriter.py", line 80, in write_pysource
    pycode, rused = convert_to_python(pcode, d.form, incl_carry)
  File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/power_pseudo.py", line 275, in convert_to_python
    tree = gsc.compile(pcode, mode="exec", filename="string")
  File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/pseudo/parser.py", line 979, in compile
    tree = self.parser.parse(code)
  File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/pseudo/parser.py", line 949, in parse
    result = self.parser.parse(code, lexer=self.lexer, debug=self.debug)
  File "/home/jacob/.virtualenvs/libre-riscv-venv/lib/python3.8/site-packages/ply/yacc.py", line 333, in parse
    return self.parseopt_notrack(input, lexer, debug, tracking, tokenfunc)
  File "/home/jacob/.virtualenvs/libre-riscv-venv/lib/python3.8/site-packages/ply/yacc.py", line 1201, in parseopt_notrack
    tok = call_errorfunc(self.errorfunc, errtoken, self)
  File "/home/jacob/.virtualenvs/libre-riscv-venv/lib/python3.8/site-packages/ply/yacc.py", line 192, in call_errorfunc
    r = errorfunc(token)
  File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/pseudo/parser.py", line 920, in p_error
    raise SyntaxError(p)
SyntaxError: LexToken(LT,'<',1,0)
make: *** [Makefile:18: pywriter] Error 1