Some instructions, before they're available in SVP64, should have the corresponding scalar versions. This list includes fsins, fcoss, ternlogi and other bit manipulation functions. These can and should be added as standalone usual 32-bit instructions into binutils, and be marked as draft ones (available via a special compiler switch). Until OPF ISA WG approves these instructions, they should be kept as draft; anyway, even as draft ones, they can be re-used by SVP64. Also, this part can and should be submitted as a standalone patch (or series of patches), outside of SVP64 patchset.
Status: implemented fsins, fsins., fcoss, fcoss., ternlogi, ternlogi. instructions. As for grev* instructions, I've started implemented these, but they in current form are fundamentally broken and need either two forms or a more substitution (e.g. the suggested grevlut). For now these are deferred. I have a backup series of patches which introduce two XB forms (XB and XBI respectively), but, there's an agreement, I'll postpone these. I'm moving towards tests, then.
FYI, I re-checked more in details. So, from binutils point of view: 1. Add XBM5 form (bit manipulation 5-bit). 2. Add XBM6 form (bit manipulation 6-bit). 3. Add XBI5 operand (same as SH/EVUIMM/FC/UIM5 operands). 4. Add XBI6 operand (same as SH16/DGM/DCM operands). All this discrepancy thanks to grevi/grevi. instructions. So, I'd rather prefer to see something more generic.
https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=be772522aaeaddfb213823cef9a0c0b871359d07 check this table, basically XB-Form can indeed be used for the 6-bit, and there's also an X-Form using SH which can be used. fields.txt 39 # 1.6.7 X-FORM 40 |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | ... 54 | PO | RS | RA | SH | XO |Rc | 163 # 1.6.15 XB-FORM 164 |0 |6 |11 |16 |22 |31 | 165 | PO | RT | RA | XBI | XO |Rc | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isatables/fields.text;h=eb962688ca674db58b65100a159c1b20cfbbb886;hb=e4142b9e970ae21639ed5a8884d193f57ffc463a#l294
OK, corrections: 1. Only grevi/grevi. need a tuning (XBI operand which is the same as SH16/DGM/DCM). 2. The rest is going to use RB.
Still, the XO part is different, so two forms.
/* An XBM5 form instruction. */ #define XBM5(op, xop, rc) \ (OP (op) \ | ((((uint64_t)(xop)) & 0x3ff) << 1) \ | (((uint64_t)(rc)) & 1)) #define XBM5_MASK XBM5 (0x3f, 0x3ff, 1) /* An XBM6 form instruction. */ #define XBM6(op, xop, rc) \ (OP (op) \ | ((((uint64_t)(xop)) & 0x1ff) << 1) \ | (((uint64_t)(rc)) & 1)) #define XBM6_MASK XBM5 (0x3f, 0x1ff, 1) #define XBI5 SH { 0x1f, 11, NULL, NULL, 0 }, #define XBI6 SH16 { 0x3f, 10, NULL, NULL, 0 }, {"grev", XBM5(5,150,0), XBM5_MASK, DRAFT, PPCVLE, {RT, RA, RB}}, {"grev.", XBM5(5,150,1), XBM5_MASK, DRAFT, PPCVLE, {RT, RA, RB}}, {"grevw", XBM5(5,182,0), XBM5_MASK, DRAFT, PPCVLE, {RT, RA, RB}}, {"grevw.", XBM5(5,182,1), XBM5_MASK, DRAFT, PPCVLE, {RT, RA, RB}}, {"grevi", XBM6(5,214,0), XBM6_MASK, DRAFT, PPCVLE, {RT, RA, XBI6}}, {"grevi.", XBM6(5,214,1), XBM6_MASK, DRAFT, PPCVLE, {RT, RA, XBI6}}, {"grevwi", XBM5(5,246,0), XBM5_MASK, DRAFT, PPCVLE, {RT, RA, XBI5}}, {"grevwi.", XBM5(5,246,1), XBM5_MASK, DRAFT, PPCVLE, {RT, RA, XBI5}},
The current state: fsins/fcoss/ternlogi are ready, both implementation and tests. I'll raise a standalone task on grev*.
A note to future self: branch is ppc-draft.