Bug 834 - binutils: support draft fsins/fcoss/ternlogi instructions
Summary: binutils: support draft fsins/fcoss/ternlogi instructions
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Dmitry Selyutin
Depends on:
Blocks: 577
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Reported: 2022-05-14 16:54 BST by Dmitry Selyutin
Modified: 2022-09-15 17:44 BST (History)
3 users (show)

See Also:
NLnet milestone: NLNet.2019.10.032.Formal
total budget (EUR) for completion of task and all subtasks: 725
budget (EUR) for this task, excluding subtasks' budget: 725
parent task for budget allocation: 577
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
[ghostmansd] amount=500 submitted=2022-05-17 paid=2022-07-07 [lkcl] amount = 225 submitted = 2022-06-16 paid = 2022-09-06


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Description Dmitry Selyutin 2022-05-14 16:54:04 BST
Some instructions, before they're available in SVP64, should have the corresponding scalar versions. This list includes fsins, fcoss, ternlogi and other bit manipulation functions. These can and should be added as standalone usual 32-bit instructions into binutils, and be marked as draft ones (available via a special compiler switch). Until OPF ISA WG approves these instructions, they should be kept as draft; anyway, even as draft ones, they can be re-used by SVP64. Also, this part can and should be submitted as a standalone patch (or series of patches), outside of SVP64 patchset.
Comment 1 Dmitry Selyutin 2022-05-15 14:49:08 BST
Status: implemented fsins, fsins., fcoss, fcoss., ternlogi, ternlogi. instructions. As for grev* instructions, I've started implemented these, but they in current form are fundamentally broken and need either two forms or a more substitution (e.g. the suggested grevlut).
For now these are deferred. I have a backup series of patches which introduce two XB forms (XB and XBI respectively), but, there's an agreement, I'll postpone these. I'm moving towards tests, then.
Comment 2 Dmitry Selyutin 2022-05-15 15:44:15 BST
FYI, I re-checked more in details. So, from binutils point of view:
1. Add XBM5 form (bit manipulation 5-bit).
2. Add XBM6 form (bit manipulation 6-bit).
3. Add XBI5 operand (same as SH/EVUIMM/FC/UIM5 operands).
4. Add XBI6 operand (same as SH16/DGM/DCM operands).

All this discrepancy thanks to grevi/grevi. instructions. So, I'd rather prefer to see something more generic.
Comment 3 Luke Kenneth Casson Leighton 2022-05-15 15:48:54 BST

check this table, basically XB-Form can indeed be used for
the 6-bit, and there's also an X-Form using SH which can
be used.


  39 # 1.6.7 X-FORM
  40    |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
  54    | PO   |       RS      |    RA       |    SH       |   XO |Rc  |

 163 # 1.6.15 XB-FORM
 164    |0     |6    |11    |16    |22    |31 |
 165    | PO   |  RT |   RA |  XBI |   XO |Rc |

Comment 4 Dmitry Selyutin 2022-05-15 16:02:43 BST
OK, corrections:
1. Only grevi/grevi. need a tuning (XBI operand which is the same as SH16/DGM/DCM).
2. The rest is going to use RB.
Comment 5 Dmitry Selyutin 2022-05-15 16:04:24 BST
Still, the XO part is different, so two forms.
Comment 6 Dmitry Selyutin 2022-05-15 16:10:47 BST
/* An XBM5 form instruction. */
#define XBM5(op, xop, rc)			\
  (OP (op)					\
   | ((((uint64_t)(xop)) & 0x3ff) << 1)		\
   | (((uint64_t)(rc)) & 1))
#define XBM5_MASK	XBM5 (0x3f, 0x3ff, 1)

/* An XBM6 form instruction. */
#define XBM6(op, xop, rc)			\
  (OP (op)					\
   | ((((uint64_t)(xop)) & 0x1ff) << 1)		\
   | (((uint64_t)(rc)) & 1))
#define XBM6_MASK	XBM5 (0x3f, 0x1ff, 1)

#define XBI5 SH
  { 0x1f, 11, NULL, NULL, 0 },

#define XBI6 SH16
  { 0x3f, 10, NULL, NULL, 0 },

{"grev",	XBM5(5,150,0),	XBM5_MASK,	DRAFT,	PPCVLE,	{RT, RA, RB}},
{"grev.",	XBM5(5,150,1),	XBM5_MASK,	DRAFT,	PPCVLE,	{RT, RA, RB}},
{"grevw",	XBM5(5,182,0),	XBM5_MASK,	DRAFT,	PPCVLE,	{RT, RA, RB}},
{"grevw.",	XBM5(5,182,1),	XBM5_MASK,	DRAFT,	PPCVLE,	{RT, RA, RB}},
{"grevi",	XBM6(5,214,0),	XBM6_MASK,	DRAFT,	PPCVLE,	{RT, RA, XBI6}},
{"grevi.",	XBM6(5,214,1),	XBM6_MASK,	DRAFT,	PPCVLE,	{RT, RA, XBI6}},
{"grevwi",	XBM5(5,246,0),	XBM5_MASK,	DRAFT,	PPCVLE,	{RT, RA, XBI5}},
{"grevwi.",	XBM5(5,246,1),	XBM5_MASK,	DRAFT,	PPCVLE,	{RT, RA, XBI5}},
Comment 7 Dmitry Selyutin 2022-05-17 10:34:25 BST
The current state: fsins/fcoss/ternlogi are ready, both implementation and tests. I'll raise a standalone task on grev*.
Comment 8 Dmitry Selyutin 2022-05-17 12:45:51 BST
A note to future self: branch is ppc-draft.