Before setvl/svstep/svshape/svremap instructions can be submitted, we must cover these with as+objdump tests, as is common in binutils repository.
OK, setvl test is ready; proceeding to the next ones.
Luke, I've increased the budget as usual so that it can be split, I hope you're OK to split it?
The tests are mostly ready; however, I'm kinda in doubts regarding size of the tests, so I decided to raise the question on the mailing list.
(In reply to Dmitry Selyutin from comment #3)
> The tests are mostly ready; however, I'm kinda in doubts regarding size of
> the tests, so I decided to raise the question on the mailing list.
amusing that the reply says it's under 1/10th the size of some of
the other unit tests submitted
(In reply to Luke Kenneth Casson Leighton from comment #4)
> amusing that the reply says it's under 1/10th the size of some of
> the other unit tests submitted
Yeah I've also been impressed. :-)
Alan keeps silence, so I will publish the autogenerated tests and wait for a reply there. This cannot be committed until FSF completes the copyright assignment procedures, though. Still, this at least is something to start with.
The script I wrote to generate the tests was quick and dirty, and does not reuse openpower-isa, like it should. It simply relies on my intimate knowledge of pysvp64asm. Still, I think it is sufficient for the first iteration. The correct way to approach this issue is to dive into instruction forms to parse operands, consider their bit-layout and generate tests automatically, as well as binutils operands. Task 838 should give us a good start.
I've just submitted the corresponding patches to binutils mailing list.
With this in mind, the only thing that blocks us is FSF copyright assignment. I've filed it on May 25, but received no reply yet. On Jun 17, I've raised the question on state of the art on fsf-records at GNU org, but they also keep silence. Any ideas on what to do next?
That said, I assume the technical part is completed and I can submit RFP. Luke, do you have any objections?
(In reply to Dmitry Selyutin from comment #7)
> I've raised the question on state of the art on fsf-records at GNU org, but
> they also keep silence. Any ideas on what to do next?
i've emailed copyright-clerk for you and cc'd you (and alexandre)
> That said, I assume the technical part is completed and I can submit RFP.
> Luke, do you have any objections?
none at all, go for it.
this needs a little work, dmitry:
* main spec https://libre-soc.org/openpower/sv/
* svp64 https://libre-soc.org/openpower/sv/svp64
* setvl https://libre-soc.org/openpower/sv/setvl/
* remap https://libre-soc.org/openpower/sv/remap/
SV (Simple-V) is a strict RISC-paradigm Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit Prefixed instruction format implementing SV. Funded by NLnet through EU Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly submitted via the OpenPOWER Foundation ISA Working Group via the newly-created External RFC Process.
Yet another revision of the patches. This time, except for addition of svindex instruction, the changes are rather cosmetic (fixed the links, renamed the field, etc.).
the actual tests are now written
Dmitry i am re-submitting this via the "secret" URLs
in one single combined RFP covering #847 #857 and #867
and updating the submitted date to 2022-07-19 on all 3.