Bug 862 - setvl Vertical-First mode issues with predicates, extend setvl to 64 bit
Summary: setvl Vertical-First mode issues with predicates, extend setvl to 64 bit
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/openpower/sv/setvl
Depends on:
Blocks:
 
Reported: 2022-06-17 19:09 BST by Luke Kenneth Casson Leighton
Modified: 2022-06-18 10:24 BST (History)
1 user (show)

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Description Luke Kenneth Casson Leighton 2022-06-17 19:09:03 BST 
predicates in Horizontal-First Mode are loaded at the start of each instruction.
for Vertical-First this is a problem.
Comment 1 Luke Kenneth Casson Leighton 2022-06-17 19:45:02 BST 
https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=6cac17aa4a16c30c337a26cb083138d5fbc0ef74

here was an idea of having a CTR reading mode.  VF mode needs some bits
to say which preficates are to be protected (made read-only).  therefore
swap vf with ct bit, and move vf mode to 24 bit RM.

then, add bits 4 for r3 r10 r30 CRf
then, allow CR Predicate to be selected starting
from CR16,CR32,CR48,CR64 (2 bits)
Comment 2 Luke Kenneth Casson Leighton 2022-06-18 10:24:58 BST 
given that VF mode only uses a single bit this is fine.  that will be a single
CRf in CR Predication.