Continuation of work started in https://bugs.libre-soc.org/show_bug.cgi?id=236
Blocked on obtaining more budget for work.
I just thought of a way to add atomic ops that don't need memory model work: we simply define them in terms of the existing instruction sequences for the atomic ops. this also means they are trivially interoperable with all existing atomic ops.
e.g. relaxed fetch_add is currently:
# addr in r3, addend in r4, result in r5
lbarx 5, 0, 3
add 6, 4, 5
stbcx. 6, 0, 3
bne 0, .LBB0_1
so amoadd r5, r4, r3 would be defined to be equivalent to the above code (except not modifying CR0 or r6)
(In reply to Jacob Lifshay from comment #1)
> I just thought of a way to add atomic ops that don't need memory model work:
> we simply define them in terms of the existing instruction sequences for the
> atomic ops.
this saves us a lot of work and saves OPF and IBM a lot of work verifying the new instructions work in the memory model, the only problem is they may be slower than necessary for C++11's memory model.
LLVM may be changing how it lowers relaxed loads to include a dummy branch:
We should take the outcome of that into account when designing our atomic instructions.