couldn't find a bug for this, so making one.
ld/st with shift isn't very useful for rt = mem((ra << sh) + imm) unless imm is >25-bits or so, so instead i think the ops we'll want are (only listing loads here, stores are analogous):
rt = mem(pc + (rb << sh) + imm) -- can be encoded by ra=0
rt = mem(ra + (rb << sh) + imm)
we'll also want a way to enable bounds checking and base addr. addition for webassembly, so imho we reserve the max sh value (for 3-bit, that'd be sh=7) to enable wasm addressing mode instead of shifting. for details, see https://bugs.libre-soc.org/show_bug.cgi?id=585
we could alternatively reserve sh=0 for wasm, since that's redundant with the existing ld/st ops and that allows sh to reasonably be only 2 bits if we're low on space. imho reserving sh=0 seems like the best idea in retrospect.