Bug 940 - SVP64 LD/ST auto-increment mode (working with LDST-update)
Summary: SVP64 LD/ST auto-increment mode (working with LDST-update)
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/openpower/sv/ldst/
Depends on:
Reported: 2022-10-03 17:16 BST by Luke Kenneth Casson Leighton
Modified: 2022-10-12 10:27 BST (History)
1 user (show)

See Also:
NLnet milestone: ---
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation:
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:


Note You need to log in before you can comment on or make changes to this bug.
Description Luke Kenneth Casson Leighton 2022-10-03 17:16:20 BST
the 68000 PDP8 PDP11 and 6600 all had auto-increment addressing modes.
Power ISA has LDST-with-update which is not quite the same but almost:
update-with-immediate on a Vector advances by the immediate, but has
an initial "one too many adds"

autoincrementing should use the EA *before* the add is performed
(i.e. just RA) as an option.  thus on loop exit RA is set to
point to where the *next* batch starts.
Comment 1 Luke Kenneth Casson Leighton 2022-10-03 17:45:18 BST
in LD/ST-immediate there is a mode-combination reserved, which can be used
for saying "use RA only as the EA, but write out (RA+imm) as the update".

this is a significant change as it means modifying the pseudocode:

    ea <- RA+D
    if preincrement then EA <- ea
    else                 EA <- RA
    RT -< MEM(EA, sz)
    RA <- ea

with a default "preincrement=1" in Scalar ISA