Bug 986 - SVP64 LD/ST format simplification
Summary: SVP64 LD/ST format simplification
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/openpower/sv/ldst/
Depends on:
Blocks: 952
  Show dependency treegraph
Reported: 2022-12-11 15:47 GMT by Luke Kenneth Casson Leighton
Modified: 2022-12-11 15:50 GMT (History)
1 user (show)

See Also:
NLnet milestone: NLnet.2022-08-051.OPF
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation: 952
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:


Note You need to log in before you can comment on or make changes to this bug.
Description Luke Kenneth Casson Leighton 2022-12-11 15:47:17 GMT
realisation after adding post-increment mode that LDST needs to be

* bit 0: post-increment
* bit 1: element-strided
* bit 2: Fault-First in LDST-Imm, SEA in LDST-Idx
* bit 3: dz
* bit 4: sz

this is a huge simplification but also removing modes that really
should be associated with Arithmetic/CRops, otherwise LDST becomes