XLEN exactly as is in RISC-V: RV32 RV64 RV128 also proposing to add 8 and 16-bit
submitted to OPF ISA WG 28th dec 2022 [[OPF][ISA] #1516] https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/rfc/ls005.mdwn;h=f19cf7fc5c9f9799e98135198ee9ed1e52883a35;hb=f86dee196769951c8fd3cc93739f9dceb9ca7d9e