The first NLnet grant allowed us to create IEEE754 FP pipelines,
which now need integration into the Libre-SOC Core, and suitable
unit tests created. It will add approximately 60 new instructions
for Power ISA 3.0 SFFS Compliancy. second priority is Power ISA v3.1

----------------------------------------------------------------

To-do list:

(this doesn't include formal proofs, which a lot of will be complex enough to blow out our budget and/or not even run in a reasonable amount of time)

cost estimates:
* NOT COMPLETED AT ALL: make educated guess how much code will be needed
  * TODO: comment #6 and other comments (which you need to track down
          and re-read jacob) regarding getting FP into TestIssuer.
          without TestIssuer supporting the FP pipeline there *is* no
          FP pipeline. this set of tasks *includes documenting* of
          TestIssuer and how it fits together, finding checking
          and then updating the existing page.
  * TODO: plan out modifications to LDSTCompUnit, integrating DOUBLE/SINGLE
          into them, coordinating with Cesar ensuring that the Formal Proof
          plans are not disrupted (TODO: find the bugreport, link it here,
          link it to this bugreport and increase cesar's budget up again
          to cover the additional work)

  * DONE: done for everything but:
    * fptrans
      * huge, needs to be split into much smaller subtasks.
        it's enough work that, except for the tasks already split out 
        (recip/[r]sqrt/mod/rem and fminmax) we should probably eliminate
        it entirely from this grant due to being lower priority and difficult.
      * will figure out only if we have budget left over from other tasks
* DONE: translate code size estimates to monetary amounts.
  using conversion factor of 27 days per 1000 lines of code, estimated in:
  https://lists.libre-soc.org/pipermail/libre-soc-dev/2023-August/005607.html
  using EUR 3000/mo from:
  https://lists.libre-soc.org/pipermail/libre-soc-dev/2023-August/005592.html
  this comes out as EUR 2.70 per line of code, assuming a month is 30 days.
  I then rounded budgets to the nearest EUR 100

====================
subtasks we're doing
====================

Needed for v3.0/v3.1-without-PO1:

* DONE: add FPSCR and rounding-mode definitions to ieee754fpu
  https://bugs.libre-soc.org/show_bug.cgi?id=1135
  * 265 lines of code 70 lines of tests
  * rounded to EUR 900
* TODO: add FPSCR and FP registers and dependency-tracking to soc.git
  * probably 100 lines of code with 100 lines of tests
  * rounded to EUR 1400
* TODO: add PowerISA SINGLE/DOUBLE conversion functions
  * (not the same as ieee 754 conversion)
  * 200 lines of code with 100 lines of tests
  * rounded to EUR 1600
* TODO: add FP loads to soc.git
  * 200 lines of code with 200 lines of tests
  * lf[s/d][u][x]
  * lfiwax/lfiwzx
  * rounded to EUR 1900
* TODO: add FP stores to soc.git
  * 200 lines of code with 200 lines of tests
  * stf[s/d][u][x]
  * stfiwx
  * rounded to EUR 1900
* TODO: FP move/sign-bit-manipulation
  * fmr[.]
  * fneg[.]/fabs[.]/fnabs[.]
  * fcpsgn[.]
  * probably 100 lines of code with 50 lines of tests
  * rounded to EUR 500
* TODO: FP add/sub
  * fadd[s][.]/fsub[s][.] using existing pipelines
    * probably 100 lines with 100 lines of tests
  * add FPSCR/rounding support to add/sub pipeline
    * probably 200 lines with 100 lines of tests (due to rounding modes)
  * rounded to EUR 2600
* TODO: FP select
  * probably 100 lines with 50 lines of tests
  * fpsel[.]
  * simple enough that I don't think we even need a ieee754fpu pipeline
  * doesn't interact with FPSCR except for writing CR1 when Rc=1
  * rounded to EUR 400
* TODO: FPSCR manipulation
  * probably 300 lines with 200 lines of tests
  * mffs[.]
  * mffsce[.]
  * mffsc[d]rn[i]
  * mffsl
  * mcrfs
  * mtfsf[i][.]
  * mtfsb[0/1][.]
  * rounded to EUR 1400

=============================
not doing as part of this bug
=============================

(just here since I already did the budgeting work)

(overlaps with https://bugs.libre-soc.org/show_bug.cgi?id=1026#c0, we need to resolve what goes where)

Needed for v3.0/v3.1-without-PO1:

* TODO: FP store double pair
  * 300-500 lines of code with 400 lines of tests
  * stfdp[x]
  * stores are part of SFFS subset, loads are not according to v3.1B Appendix H
  * rounded to EUR 2200
* TODO: FP merge words
  * fmrgew
  * fmrgow
  * probably 100-200 lines of code with 50 lines of tests
  * rounded to EUR 500
* TODO: FP mul/fma
  * fmul[s][.]/f[n]madd[s][.]/f[n]msub[s][.] using existing pipelines
    * probably 2-300 lines with 200 lines of tests
  * add FPSCR/rounding support to mul/fma pipeline
    * probably 200 lines with 100 lines of tests (due to rounding modes)
  * rounded to EUR 3100
* TODO: FP div/sqrt/fre/frsqrte
  * fdiv[s][.]/fsqrt[s][.]/fre[s][.]/frsqrte[s][.] using existing giant div core
    (fre[s][.]/frsqrte[s][.] are full accuracy ops since that's easiest since
    we already need the full accuracy ops for fptrans and we already have a
    pipeline that does the core operation.)
    * probably 300-400 lines with 300 lines of tests
  * create new much smaller FSM pipeline suitable for small cores
    (the giant pipeline won't fit on most our FPGAs),
    basically taking all the giant div core and converting each stage
    to a FSM state. This includes fmod*/fremainder*/frecip*/frsqrt* since
    those are simple on top of the existing div/sqrt/rsqrt logic.
    * probably 500 lines with 200 lines of tests
  * add FPSCR/rounding support to div/sqrt/rsqrt pipeline
    * probably 200 lines with 100 lines of tests
  * rounded to EUR 4500, 1800 for just using existing giant div core,
    3600 without full rounding support
* TODO: FP test for SW div/sqrt
  * ftdiv/ftsqrt
    * probably 150 lines with 50 lines of tests
  * rounded to EUR 800
* TODO: FP round to single
  * frsp[.]
  * add FPSCR/rounding support
  * probably 2-300 lines with 300 lines of tests
  * rounded to EUR 1500
* TODO: FP convert from integer
  * https://bugs.libre-soc.org/show_bug.cgi?id=1137
  * needs fcfi* in ISACaller -- 500 lines with 200 lines of tests
    * mostly copy-paste, so only counting 300 lines total
  * probably 200-400 lines for pipelines/insns
  * create ctfpr pipeline, it can be used (perhaps with slight
    modifications) for all the fcfi* insns too.
  * this covers all of:
    * fcfid[u][s][.]
    * ctfpr*
  * rounded to EUR 1900
* TODO: FP convert to integer
  * https://bugs.libre-soc.org/show_bug.cgi?id=1136
  * needs fcti* in ISACaller -- 500 lines with 200 lines of tests
    * mostly copy-paste, so only counting 300 lines total
  * probably 400-500 lines for pipelines/insns
  * create cffpr pipeline, it can be used (perhaps with slight
    modifications) for all the fcti* insns too.
  * this covers all of:
    * fcti[d/w][u][z][.]
    * cffpr*
  * rounded to EUR 2000
* TODO: FP round to integer (FP to FP, not FP to int)
  * probably 200 lines with 100 lines of tests
  * fri[n/p/z/m][.]
  * add FPSCR support
  * rounded to EUR 800
* TODO: FP compare
  * probably 200 lines with 100 lines of tests
  * fcmp[u/o]
  * add FPSCR support
  * rounded to EUR 800

Needed for Libre-SOC extensions (stuff that's in openpower-isa):

* TODO: fmvis/fishmv
  * probably 100 lines with 50 lines of tests
  * rounded to EUR 400
* SEE ABOVE: c[ft]fpr* (covered by tasks above for FP convert from/to integer)
* TODO: m[ft]fpr*
  * probably 150 lines with 50 lines of tests
  * rounded to EUR 500
* TODO fptrans insns (fminmax*, fsqrt*/frsqrt*, frecip*, fmod*/fremainder*
  are split out into separate tasks)
  * easily multiple thousands of lines of code, should be split up further into
    sub-sub-tasks
* SEE ABOVE: fsqrt*/frsqrt*, frecip*, fmod*/fremainder* (covered by
  task above for FP div/sqrt/fre/frsqrte)
* TODO: fminmax*
  * probably 300 lines with 100 lines of tests
  * https://bugs.libre-soc.org/show_bug.cgi?id=1134
  * rounded to EUR 1100
* TODO: FFT/DCT FP ops
  * fdmadds/ffadd/ffdiv[s]/ffmadds/ffmsubs/ffmul[s]
    /ffnmadds/ffnmsubs/ffsub[s] in openpower-isa
  * probably 500 lines with 300 lines of tests
  * rounded to EUR 2200