missing from ISACaller is the fmv/fcvt/fcfids/ftst instructions that are needed for even doing hardware tests, these need adding * DONE: add fields and pseudo-code for fmv*/fcvt* * DONE: add unit tests for fmv*/fcvt* * DONE: add unit tests for fcvttg * DONE: add unit tests for fcvttgo. * DONE: add unit tests for fcvtfg[s] * DONE: add unit tests for fmv* * DONE: add SVP64 unit tests * DONE: add parser support for FPSCR attributes and SetFX * DONE: add simulator support for FPSCR bug #1025 * DONE: add ExpectedState support for FPSCR bug #1025 * DONE: remove Rc=1 support for fmvfg* * DONE: test sprs and msr on traps * DONE: implement enough of the bfp_* functions for fcvt to work * DONE: bfp_* functions for fcvttg* * DONE: bfp_* functions for fcvtfg* * DONE: change SelectableMSB0Fraction so bit 0 is the lsb integer bit, bit 1 is the first fractional bit * DONE: decide if the bfp_* functions should be translated from english prose to python or pseudocode (see comment #21) they're getting translated to pseudocode, will be submitted sometime later Needs to be split out to another bug: * TODO: implement missing PowerISA v3.1 FPU ops bug #1025 * TODO: implement ftst instructions
(In reply to Luke Kenneth Casson Leighton from comment #0) > missing from ISACaller is the fmv/fcvt/fcfids/ftst instructions > that are needed for even doing hardware tests, these need adding this task should be split more, since the above list is like 15 mostly-independent instructions...
(In reply to Jacob Lifshay from comment #1) > (In reply to Luke Kenneth Casson Leighton from comment #0) > > missing from ISACaller is the fmv/fcvt/fcfids/ftst instructions > > that are needed for even doing hardware tests, these need adding > > this task should be split more, since the above list is like 15 > mostly-independent instructions... eek! hmmm then there's nowhere near enough budget for it. let me look for a way to reduce the scope - probably taking fcfids/ftst off the list and moving them elsewhere.
I allocated draft opcode encodings for fmvfg[s]/fmvtg[s]/fcvtfg[s]/fcvttg[o][s] I verified fcvttg[s] don't collide with anything in v3.1B since they're not on the fptrans tables. https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=0b4268b20e6e4c911c80e5e8011b737af3fd6d17;hp=347b76c4d5842e1f4898943553687d1dece6db3f commit 0b4268b20e6e4c911c80e5e8011b737af3fd6d17 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 18:35:05 2023 -0700 fix allocated mnemonic commit 1102cb2788edf05cc430912ebb06884bb9fea7f0 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 18:33:20 2023 -0700 allocate fmv/fcvt draft opcodes I made space by commenting out all the fmin/fmax ops since they're being replaced, ghostmansd can finish that off later. Also some misc cleanup/fixes: https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=e96f99d0bd0e2ff0a8935c842ce01fd4065c2f8e commit e96f99d0bd0e2ff0a8935c842ce01fd4065c2f8e Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 18:13:13 2023 -0700 remove testing with INSNDB=true since that now does nothing different commit 9c65658cfa1bd5b4f0023df19afbb113d27ecad0 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 18:08:46 2023 -0700 comment fmin*/fmax* since they're being replaced with fminmax and to make space for fmv/fcvt commit a9409bae79b6ce6a374b14f0e9f48cab7c313ad3 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 18:04:36 2023 -0700 fix non-zero assembly operands being zero commit caea5e57bb51caa04ef6038d9f6176db22588157 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 17:13:24 2023 -0700 update SV csvs
I added all the pseudo-code and fields.txt stuff, will add unit tests next. while doing that, I got fed up with the terrible pseudo-code syntax error reports and fixed that to use Python's normal location reporting, which has the added benefit that IDEs understand that error format and can go straight to the syntax error in the file. errors now look like: File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/pseudo/parser.py", line 873, in p_error self.input_text) File "/home/jacob/projects/libreriscv/openpower-isa/src/openpower/decoder/pseudo/lexer.py", line 21, in raise_syntax_error input_text[line_start:line_end])) File "/home/jacob/projects/libreriscv/openpower-isa/openpower/isa/condition.mdwn", line 119 CR[BT+32] <- CR[BA+32] | ¬CR[BB+32] ERROR HERE ^ SyntaxError: LexToken(NAME,'ERROR',119,155) make: *** [Makefile:18: pywriter] Error 1 https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=2aa59d113549e4e7582b6d9b4d8ddcd09d63164c commit 2aa59d113549e4e7582b6d9b4d8ddcd09d63164c Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 21:41:31 2023 -0700 fix forgotten stuff from last commit commit 9255849db0fa7b5aa703d1bde0ee7257579ffb21 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 21:27:06 2023 -0700 add fcvt/fmv -- no tests yet commit 3cdf23bcd2851ba8683e6782856398b98e4aded5 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 21:25:42 2023 -0700 support calling functions with no args in pseudocode commit 8e0f6ea81295acbf72a14d8310fb3cd48ba01ba5 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 21:15:45 2023 -0700 show actual mdwn source location in backtrace when parser raises SyntaxError commit 10ba7151784dc708837c55d92528d7c3ca022920 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 21:08:49 2023 -0700 move Assign to parser class in prep for improving syntax error reporting commit 9c588688ac2b354986062fb275c329db4eeb4db1 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 18:55:29 2023 -0700 add all fmv*/fcvt* fields commit e0160c09fd084659a64ad591f2202055c43fbde4 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 3 18:48:46 2023 -0700 split XO-Form's RA field in prep for adding fcvttg[o][s] also reformat cuz we can
I added some fmv/fcvt tests, copying some toint32 tests from V8, however I ran into a roadblock: FPSCR is not implemented -- Luke, can you add that? it seems likely to be difficult for me since it isn't actually an SPR, it's a completely custom register. I also added some misc. validity checking -- checking that fields.txt lines up correctly and checking that generated .py files aren't missing from .gitignore https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=c8b2c5d2c984cc444880187679c2a9589bae0526 commit c8b2c5d2c984cc444880187679c2a9589bae0526 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 4 19:19:29 2023 -0700 add initial fmv/fcvt tests, though they're broken due to FPSCR being unimplemented commit d953b17515cce377efcf77544d15d3639aa3d974 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 4 17:55:15 2023 -0700 add check that generated .py files are in .gitignore commit 496c01f81a9afda2edca268e93d5f0fa785a220a Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 4 17:34:27 2023 -0700 verify fields.txt forms' field separators ('|') line up with headers'
(In reply to Jacob Lifshay from comment #5) > I added some fmv/fcvt tests, copying some toint32 tests from V8, however I > ran into a roadblock: FPSCR is not implemented -- Luke, can you add that? it's quite a lot of thought and research needed, should be done under the other task(s) adding FP pipelines. or at least part of it.
(In reply to Luke Kenneth Casson Leighton from comment #6) > (In reply to Jacob Lifshay from comment #5) > > I added some fmv/fcvt tests, copying some toint32 tests from V8, however I > > ran into a roadblock: FPSCR is not implemented -- Luke, can you add that? > > it's quite a lot of thought and research needed, should be done under > the other task(s) adding FP pipelines. or at least part of it. all I need is just the register with accessible fields, I expect that to not be super difficult for you...
(In reply to Jacob Lifshay from comment #7) > all I need is just the register with accessible fields, copy the style here https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/svstate.py;hb=HEAD i will followup by adding it to ISACaller.
i've removed 50% of the code in fpscr.py as it is massively complex and completely unnecessary, introducing a maintenance nightmare by being radically different from *all* other code that creates Fields. if you want to do this sort of thing you *need to discuss the impact first* and we discuss *and budget* for a conversion of *ALL* Fields - at the same time - to any AGREED new paradigm. please DON'T do this again, i had to spend most of my time rewriting and removing code instead of a straightforward 5 minutes adding to ISACaller and the Test API removed unnecessary complex unauthorised code https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=27d4b0da016381cb723cf07e1a01c61a2e77831e added into ISACaller https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=6f9ccd3da6bff4d596357628e60f206eb73f41f8 added to Test API https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=dad902a77535a947cc3d1f275414256dc48ad35e
I added support for accessing fields through FPSCR.RN rather than FPSCR[RN] and switched all uses of the [] syntax to use attribute syntax instead -- to avoid getting luke upset, I pushed it to the switch-to-using-fields branch instead. I also made some fixes to FieldSelectableInt (pushed to master) and cleaned up the round single code. https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=7d7cc78fcb45ba6fef00483c0f078d825fed3be1 commit 7d7cc78fcb45ba6fef00483c0f078d825fed3be1 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 00:33:42 2023 -0700 remove now-unnecessary namespace entries commit 921ef4aa0cbcc5bf15f73ce0dbc74e597912273e Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 00:31:00 2023 -0700 access XER via fields commit dc6482b845a7f809c4d08a26f3ea16ade5492f2c Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 00:30:06 2023 -0700 access FPSCR through self commit b04ec1880b731b71362cb3787a998aaf59eedb54 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 00:27:19 2023 -0700 SetFX is not a normal function -- it can assign to its input commit 433537a120e0b31adc1656eeda5b8911975b89c5 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 00:25:23 2023 -0700 switch fpcvt over to using FPSCR attributes commit 7577a3fa3809b8fe841daeb336c91541adff8825 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 00:22:57 2023 -0700 add parser support for attributes like FPSCR.RN commit b35faaa4bec67fc197ee0d78dc607e0eb0c8654d Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 00:13:08 2023 -0700 move apply_trailer into parser class commit 94d287a2a2746314edaf0a97c2257061aa025e67 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 00:10:27 2023 -0700 bypass ply's eating SyntaxErrors commit 30faac34669ce3f357c7d19f396933bebdfa36e5 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 00:06:30 2023 -0700 FPSCR.FPRF can be assigned strings commit e6cf2656e9b86fd6392d76f56149cbfb5777ca3f Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 00:05:30 2023 -0700 add XERState since XER has fields too commit 229700026d892642ed8510b95d57cd2f2d7801f0 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Mon May 8 23:10:29 2023 -0700 fix some broken FieldSelectableInt handling
(In reply to Jacob Lifshay from comment #10) > I added support for accessing fields through FPSCR.RN rather than FPSCR[RN] > and switched all uses of the [] syntax to use attribute syntax instead -- to > avoid getting luke upset, I pushed it to the switch-to-using-fields branch > instead. to be clear, I switched things like XER[SO] to XER.SO, I did not switch things like SVSTATE[32:33].
perfectly happy with all of these except for the changes to XER.SO https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=921ef4aa0cbcc5bf15f73ce0dbc74e597912273e can you please revert that. ermermermerm... *thinks*... *both* of these should not be there, because ISACaller derives *from* ISACallerHelper: @@ -847,6 +848,12 @@ class ISACallerHelper: def XLEN(self): return self.__XLEN + @property + def FPSCR(self): @@ -1268,6 +1268,10 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): def XLEN(self): return self.namespace["XLEN"] + @property + def FPSCR(self): + return self.fpscr +
no, put that back please. https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=7d7cc78fcb45ba6fef00483c0f078d825fed3be1
https://libre-soc.org/irclog/%23libre-soc.2023-05-09.log.html#t2023-05-09T10:44:36 it's never come up before as the issue has been avoided: the latex version of the spec pseudocode has to be auto-generatable (with hacks and workarounds as long as they are consistent). it was never an issue before because we did not have VAR.field syntax (FP being the very first where it's really needed). markdown-VAR.field should very obviously be translated to latex-VAR.field however if XER[SO] is converted entirely to XER.SO there is no way to know that this should be translated to the subscript latex format "XER<sub>SO</sub>" if the *specification* (the ISA WG) accepts a corresponding change from XER-subscript-SO to XER.SO *then* our markdown should be changed. please bear in mind: *EVERY* single change to the markdown represents an ***ACTUAL*** Formal Request to the OpenPOWER ISA Technical Working Group to make that exact change. the amount of work involved in that is absolutely massive: a full RFC has to be written, then proposed, then justified, then actioned, then communicated back. so please for goodness sake keep such changes to an absolute bare minimum.
Ok, second attempt on the support-fields branch: https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=a9aa701ca4cdcd245cde8f558a377f12107c710a the oldest commit listed here and everything after is the same as in comment #10, everything else has been reworked. These two commits make double2single.mdwn match the spec pdf much more closely: commit a9aa701ca4cdcd245cde8f558a377f12107c710a Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 19:30:03 2023 -0700 switch to using self.FPSCR commit 52f503447cc2a4c2b1106bb0abe8139fa6771a5d Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 19:27:41 2023 -0700 switch to using FPSCRState for double2single.mdwn @property FPSCR appears in two places, one in ISACaller where the fpscr variable is available, the other is in ISACallerHelper since that is used without ISACaller in test_caller_svp64_dct.py: commit 7a34ff20acf34834c7878fecff574d844ba8a538 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 19:16:37 2023 -0700 add self.FPSCR iirc you agreed this was fine since the XER[SO] syntax still works: commit a50eb1eb70ee305ba3091455cf1473abd4a74fb2 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 19:12:01 2023 -0700 remove now-unnecessary SO global, since XER[SO] syntax now translates to XER.SO this is new, it supports translating UC1[UC2] where UC[12] are any uppercase names to UC1.UC2 in the python, though has exceptions for GPR[RA] and similar: commit 5178364866f48cc6ddd8c18c1801a508a2d65636 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 18:54:26 2023 -0700 support FPSCR[RN] syntax that translates to FPSCR.RN this just changes XER's type to XERState, no pseudo-code changes whatsoever: commit e7a8aef7d412b25eec6f1e74c40129faf4a0bc41 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 18:48:47 2023 -0700 add support for accessing XER using XER.SO syntax -- intended for new pseudocode this and everything older are unchanged from comment #10: commit b04ec1880b731b71362cb3787a998aaf59eedb54 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 00:27:19 2023 -0700 SetFX is not a normal function -- it can assign to its input
please put that back. @@ -1250,7 +1250,6 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): 'FPSCR': self.fpscr, 'undefined': undefined, 'mode_is_64bit': True, - 'SO': XER_bits['SO'], 'XLEN': 64 # elwidth overrides }) comment 12. both of these should not be necessary, ISACaller derives from ISACallerHelper. https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=7a34ff20acf34834c7878fecff574d844ba8a538 it is definitely a bug to have an arbitrary hidden piece of state created, i.e. not from the constructor. look where DOUBLE2SINGLE is used in some of the matrix/fft unit tests. *really* do not create hidden side-effects, hunting them down in unknown python code is a total bitch, wastes vast amounts of time. it is better to force users of standalone ISACallerHelper to pass in an initial_fpscr there and to then make ISACaller initialise it (pass on the initial_fpscr argument). otherwise you have two copies of FPSCRState.
(In reply to Luke Kenneth Casson Leighton from comment #16) > please put that back. > > it is definitely a bug to have an arbitrary hidden piece of state > created, i.e. not from the constructor. https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=b024f03c258a7651893f485cc0b7e2d6e6f4c90f commit b024f03c258a7651893f485cc0b7e2d6e6f4c90f Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 22:17:49 2023 -0700 change FPSCR to a required parameter of ISACallerHelper commit c03a94a08f2d0c25aff31c0af05b7f01053c9838 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 9 21:58:02 2023 -0700 Revert "remove now-unnecessary SO global, since XER[SO] syntax now translates to XER.SO" luke wants the SO global to stay even though it's unnecessary This reverts commit a50eb1eb70ee305ba3091455cf1473abd4a74fb2.
I started implementing the binary-floating-point working format used by most of the PowerISA spec's bfp_* functions. This is complex since it needs a sliceable MSB0 real number type for `significand`, which I wrote as a wrapper around Fraction. bit 0 is the first fractional bit, since that is what the PowerISA spec expects. SelectableInt is insufficient since we can need more than 256 bits and we will want support for values that overflow beyond bit 0 to bit -1, -2, ... https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=a026c3d701109437ca75eb0b84794f5ed2ddeed7 initial data-structure code, still needs tests
(In reply to Jacob Lifshay from comment #18) > bit 0 is the first fractional bit, since that is > what the PowerISA spec expects. actually bit 0 is the lsb integer bit, bit 1 is the first fractional bit...adding a todo to fix that.
(In reply to Jacob Lifshay from comment #17) > (In reply to Luke Kenneth Casson Leighton from comment #16) > > please put that back. > > > > it is definitely a bug to have an arbitrary hidden piece of state > > created, i.e. not from the constructor. > > https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=b024f03c258a7651893f485cc0b7e2d6e6f4c90f merged to master: https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=f8b3a0048747cbeb51fff776e7a14fab8ee6c2d6
(In reply to Jacob Lifshay from comment #19) > (In reply to Jacob Lifshay from comment #18) > > bit 0 is the first fractional bit, since that is > > what the PowerISA spec expects. > > actually bit 0 is the lsb integer bit, bit 1 is the first fractional > bit...adding a todo to fix that. fixed! I also added through tests of SelectableMSB0Fraction commit 8e56c6b9468925a44aaa805ff05605ec5cc369a5 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 11 01:05:04 2023 -0700 SelectableMSB0Fraction is now basically complete and correct afaict next is adding smoke tests of the rest of fp_working_format, and deciding if we want the bfp_* functions to be manually translated from mostly english prose to pseudocode (preferred) or to python...this is *not* intended for submission to the ISA WG as a change of the spec, but just that being in pseudocode makes it easier for us to implement them. I'll add comments to that effect in the pseudocode.
(In reply to Jacob Lifshay from comment #21) > next is adding smoke tests of the rest of fp_working_format, and deciding if > we want the bfp_* functions to be manually translated from mostly english > prose to pseudocode (preferred) yes agreed. ultimately they could be submitted to the OPF ISAWG to add to the Appendix. and also run through Boris Shingarov's Formal Proof converter which is based on pywriter.py
(In reply to Luke Kenneth Casson Leighton from comment #22) > (In reply to Jacob Lifshay from comment #21) > > > next is adding smoke tests of the rest of fp_working_format, and deciding if > > we want the bfp_* functions to be manually translated from mostly english > > prose to pseudocode (preferred) > > yes agreed. ultimately they could be submitted to the OPF ISAWG > to add to the Appendix. ok, in that case I won't add the comment saying they're not intended for submission. I started implementing the required bfp_* functions. I ran into a few issues, two of which are worth mentioning: 1. I kept on running into the lack of shift operators ...they added <<< and >>> for rotate operators...shift operators are defined for the section where all the bfp_* functions are defined, so we should be able to use them there. 2. there is no truediv operator available in pseudocode -- the PowerISA spec specifies to use `/` for that, but you decided to use that for trunc_div. therefore I made operator.truediv available to pseudocode as a function. when translating to latex, we can do `/` -> `÷` and `truediv` -> `/`. commit f81a4bdb764b21be6c6d11cd2b7c2da137e00157 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 11 23:48:06 2023 -0700 add some bfp_* functions -- this isn't yet enough to run fcvt* commit 75b7af33c1aa0ef9373a44a679da87ac4171487f Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 11 23:44:51 2023 -0700 make truediv available to pseudocode technically `/` in pseudocode is supposed to be real number division, with `÷` being division with result truncated to integer, however luke decided to just use `/` for integer division in pseudocode, so we need a way to work around that. commit 0ebd4c333d0deab4a2459750124c6f41a543af96 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 11 23:43:41 2023 -0700 add bfp classification predicates commit 2fd9dc8c963af023b03e8bda07d353cf4b4d0a86 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 11 23:38:09 2023 -0700 allow assigning BFPState and SelectableMSB0Fraction values in pseudo-code commit aceb10a5053c82c35b97b9228a6af89a4e6b8a98 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 11 23:35:41 2023 -0700 add support for *_flag global variables needed by bfp_* functions commit f6fbc46dd0a4cc4dcee7c20b7d898d11b7634fa4 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 11 23:32:16 2023 -0700 make lexer replace class with class_ since it's a python keyword commit 1a6d7f573af34407b1423c0bad7b6bb4a43bc5b7 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 11 23:31:02 2023 -0700 fix SelectableMSB0Fraction's constructor commit 36ce3b2f3106e934eac9d3ad0e9f535c342da42c Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 11 23:30:12 2023 -0700 undefined is a function that needs to be called commit f88d2ee9e6fbe6b3caec214b4a035c8d294a1ff0 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 11 22:49:34 2023 -0700 fix broken FPSCR fields commit f99d9cd515995b2d628ca295bfc94a8565700c88 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 11 18:53:59 2023 -0700 Revert "add stub reset_xflags function" the function actually should be in pseudocode This reverts commit c44cd164b385a18fb635e7087c2a253c30d9c81c.
The first fcvttg tests pass! (just testing input/output for f64->i32 js conversion but not FPSCR, I copied the tests from: https://chromium.googlesource.com/v8/v8.git/+/d94dfc2b01f988566aa410ce871588cf23b1285d/test/mjsunit/toint32.js ) I still need to check FPSCR output and test all the other modes and all the other instructions. https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=74f645dd6b709dd131856a561bb85ef15a9414c8 commit 74f645dd6b709dd131856a561bb85ef15a9414c8 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri May 12 18:06:47 2023 -0700 add rest of bfp_* helpers needed to run fcvt js test commit f1208d652801808701eb882758149a7d7bcc17d2 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri May 12 18:05:24 2023 -0700 fix `even` polarity in bfp_ROUND_TO_INTEGER commit 815bb903449cf3effe852d18e0245690939d1ab2 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri May 12 18:04:39 2023 -0700 ignore FPSCR in fcvt js test commit 3cbb0b78f429b99d6dfaf6048319dfc5be53cdd1 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri May 12 18:03:58 2023 -0700 allow ignoring FPSCR in tests commit 8202e331d18bd865c30e87ac08ee43b11c97dba6 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri May 12 18:02:56 2023 -0700 pow should not become self.pow commit 1b8039a268e870d6aeab29afd6c3e3a470df2e60 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri May 12 17:59:40 2023 -0700 fix bugs in fcvt* pseudocode
I added tests for the FPSCR output generated by the JS tests, previously FPSCR was completely ignored. I fixed fcvttg* FPSCR computation and while I was at it, I changed the overflow output to only be set when the result actually overflows rather than just rounds -- previously overflow was set whenever the input value wasn't equal to the output value, now overflow is set only when the rounded (trunc/floor/ceil/etc.) input value isn't equal to the output value. https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=fe2d79d41248ccd0f773298f9f0766bae345bc30 I also changed FPSCRState to act more like the FPSCR register in PowerISA -- it has 2 bits that are hardwired to always be computed from the other bits, so I changed FPSCRState to also do that, though there is an opt-out flag you can pass if you have a fpscr value and just want to decode it without changing the value. https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=89a6d373d313df05d8a424178974d9593839f622 commit 89a6d373d313df05d8a424178974d9593839f622 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Mon May 15 23:53:40 2023 -0700 fcvttg*: test FPSCR output commit 0f21df082b191f27c61de61e1746d842e9685dcf Author: Jacob Lifshay <programmerjake@gmail.com> Date: Mon May 15 23:50:52 2023 -0700 fix fcvttg* overflow/FPSCR computation commit 11c3ed1b9b3fc40de0ac6910a4453ce73767371c Author: Jacob Lifshay <programmerjake@gmail.com> Date: Mon May 15 23:48:28 2023 -0700 fix mis-computed exponent in bfp_CONVERT_FROM_BFP64 commit c08b2ebac840f91fc1f000c721a984293ced8f44 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Mon May 15 23:47:03 2023 -0700 make mis-matched FPSCR errors much easier to read commit d8f44c10009d84222df48f6ce6f6fd092fad0765 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Mon May 15 23:44:22 2023 -0700 fpscr: rename computed bits -> summary bits since that's what the spec uses commit c88429bb799867eb7b35f1c30e763b20c41d77ab Author: Jacob Lifshay <programmerjake@gmail.com> Date: Mon May 15 21:34:20 2023 -0700 auto-compute FPSCR exception summary bits
(In reply to Jacob Lifshay from comment #25) > I added tests for the FPSCR output generated by the JS tests, previously > FPSCR was completely ignored. > I fixed fcvttg* FPSCR computation super. > and while I was at it, I changed the > overflow output to only be set when the result actually overflows rather > than just rounds -- previously overflow was set whenever the input value > wasn't equal to the output value, now overflow is set only when the rounded > (trunc/floor/ceil/etc.) input value isn't equal to the output value. ah i forgot to mention/advise: search in caller.py for "overflow" then pay attention to the div_overflow local function parameter. if you use it, it will go into XER when OE=1. so you have to watch out in the CSV file to make sure that oe-en is *off*. also it may be better to call it "fp_overflow" or something different so that modifications or special handling in parser.py are not needed. we don't need that hassle. if however you *wanted* overflow to be set, *wanted* OE=1 to set XER then you're doing the right thing in the pseudocode :) btw i strongly suggest moving the entirety of fcvttg to an Appendix as a pywriter function. it is *far* too complex, even to write the english description needed. extensive comments - in the spirit of the "Power ISA english description" associated with each instruction pseudocode - will have to suffice. about that: it is 100% imperative to under no circumstances use personal pronouns in pseudocode code-comments or the english description or basically anywhere in the spec now that i think about it. banned words: "i we he she you your my our ours their theirs they them" and others also starting sentences with "this" are generally frowned on. "this works because the largest type we try to convert from has 53 significand bits, " --> "the largest type CONVERTED [below] has 53 significand bits" this is a style that is crucial to maintain in specifications, the only other location i have heard of where it is used is in write-ups of scientific experiments (with the additional rule not applicable here of always writing scientific experiments in "past tense").
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/fpcvt.mdwn;h=d25ba9cde097029494325eb7800306ec1cef9c02;hb=0f21df082b191f27c61de61e1746d842e9685dcf#l189 at line 189 a repeat (or similar) comment is needed on the initialisation of overflow. please add such a comment. it is not ok to expect people to read backwards in time. this is a specification. i cannot say more.
https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=593544d3e3331b2f1fb2547714b8e04996a49761 commit 593544d3e3331b2f1fb2547714b8e04996a49761 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 17:28:02 2023 -0700 rephrase to avoid personal pronouns commit de472a817591b700b7ac2dc15ebe431a23327365 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 17:16:38 2023 -0700 duplicate overflow comment as requested by luke https://libre-soc.org/irclog/%23libre-soc.2023-05-16.log.html#t2023-05-16T08:54:24 https://git.libre-soc.org/?p=libreriscv.git;a=shortlog;h=f43e51b44a95ffb2dcea3e193be0b5656f412f83 commit f43e51b44a95ffb2dcea3e193be0b5656f412f83 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 17:27:24 2023 -0700 rephrase to avoid personal pronouns commit 87e2c6cb1bdff9727177e81123037ef7574ad2fe Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 17:12:50 2023 -0700 duplicate overflow comment as requested by luke https://libre-soc.org/irclog/%23libre-soc.2023-05-16.log.html#t2023-05-16T08:54:24
I got fcvttg working, testing all conversion modes! I still need to test fcvttgo. and the other fmv*/fcvt* instructions. https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=c75dd28e637f6f555d5c6116576924812b0b9f9a commit c75dd28e637f6f555d5c6116576924812b0b9f9a Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 21:53:45 2023 -0700 fix bug in fcvttg OpenPower and saturating conversion https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=0fd5b15bf193e1a13d78f650468d53c19598f50b commit 0fd5b15bf193e1a13d78f650468d53c19598f50b Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 21:54:38 2023 -0700 test all fp -> int conversion modes commit e956c744d4b3f54d4b8dcfe0b4cc2bf5640a8ccb Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 21:52:52 2023 -0700 fix bug in fcvttg OpenPower and saturating conversion commit 20fd00f3563930152217351f96ea0ebd49e3a11c Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 21:51:39 2023 -0700 add support for setting initial FPSCR in unit tests commit 773112a9e8d031fd8f7cfb0f8ff9a69340df5f85 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 21:50:47 2023 -0700 add fp value to BFPState.__repr__ commit c67cbb78b0ec7361c507d08bc35789ba7f855eb7 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 21:50:07 2023 -0700 add more fp -> int bfp* functions commit 382ad5d3438ea8e717793440f5f00d3bbe983f11 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 21:48:57 2023 -0700 fix fp comparison commit c99586c364a1e5dfa36f18576f3a11f76cc205ba Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 21:48:04 2023 -0700 fix round nearest-even commit 6278eccf98aeb29e5bfd811c6b6534c7e8976ad2 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 19:50:13 2023 -0700 rename js_toint -> toint in preparation for adding non-js fp->int tests commit e23f7b0b354e1e968f890439ada5ff41732f7631 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 19:11:24 2023 -0700 expand fcvttg js tests to also test conversion to u32/i64/u64 commit f5632cf71d4dfd2a711b4e8c43f4f0d8c88042da Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 19:10:03 2023 -0700 add bfp_CONVERT_FROM_UI32/64 commit f22ede900715c492a142368267afbe4109e8a08b Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 16 19:07:42 2023 -0700 rename js_toint32 -> js_toint in preparation for adding u32/i64/u64 tests
this is turning out to be a lot of work so i am increasing the budget. we do have to be careful as there is supposed to be corresponding HDL for them.
(In reply to Luke Kenneth Casson Leighton from comment #30) > this is turning out to be a lot of work so i am increasing the budget. > we do have to be careful as there is supposed to be corresponding HDL > for them. yeah, I can implement hdl too, it shouldn't be all that complex, maybe 2-3 days work, assuming soc.git already has basic support for fp ops (reading/writing FPRs and FPSCR). if not, adding basic fp support should be easily justifiable as a separate task under the integrate-ieee754fpu-into-soc task. should fmvtg/fcvttg be a new FU since it reads fprs and writes gprs? same thing with fmvfg/fcvtfg.
(In reply to Jacob Lifshay from comment #31) > yeah, I can implement hdl too, it shouldn't be all that complex, maybe 2-3 > days work, assuming soc.git already has basic support for fp ops > (reading/writing FPRs and FPSCR). actually closer to 1-2 days since iirc fcvtfg basically already exists in ieee754fpu
I converted the tests to test fcvttgo. instead of fcvttg since there are too many tests (3300) to just duplicate them all. Next, I'll add a smoke-test for fcvttg/fcvttg./fcvttgo https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=c67ff65b6d660c6c1f1d258e74a41347f1328c5d commit c67ff65b6d660c6c1f1d258e74a41347f1328c5d Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 17 21:26:23 2023 -0700 test fcvttgo. instead of fcvttg commit 04ca70635b1533599249bc8cd37dab4a54e1df39 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 17 21:25:16 2023 -0700 fix CR0 output for fmvtg*/fcvttg* commit 27d3276446e219fdecec1e43e1d6d599852f15fb Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed May 17 21:24:35 2023 -0700 add fmv*/fcvt* to sv_analysis.py
(In reply to Jacob Lifshay from comment #31) > (In reply to Luke Kenneth Casson Leighton from comment #30) > > this is turning out to be a lot of work so i am increasing the budget. > > we do have to be careful as there is supposed to be corresponding HDL > > for them. > > yeah, I can implement hdl too, it shouldn't be all that complex, maybe 2-3 > days work, from when you start until when you finish please keep an accurate log! this will help you to get some feedback on whether your time-estimates are accurate. the reason i ask that is because the last one you said "it'll be 2 weeks" it turned out to be 4 months. as that is a consistent systematic mistake that you make it's important for you to get some feedback on (to yourself, by yourself) > assuming soc.git already has basic support for fp ops > (reading/writing FPRs and FPSCR). if not, adding basic fp support should be > easily justifiable as a separate task under the > integrate-ieee754fpu-into-soc task. correct, it doesn't exist at all. good idea new task. FPSCR can be added as its *own* regfile - this is important. copy style of XER. FPR likewise. see https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;hb=HEAD essential to add FPSCRRegsEnum and FPRRegs Enum: 31 # XXX MAKE DAMN SURE TO KEEP THESE UP-TO-DATE if changing/adding regs 32 from openpower.consts import StateRegsEnum, XERRegsEnum, FastRegsEnum please take GREAT CARE here, go slowly, make sure to follow process "i am thinking of doing X, please review, i have done X, please review" and WAIT for review feedback BEFORE going ahead to the next phase ok? > should fmvtg/fcvttg be a new FU since it reads fprs and writes gprs? same > thing with fmvfg/fcvtfg. ohh yes. the decision is actually made by "register profile". i.e. examine *all* pipe_data.py and based on what you see there you will find with 100% certainty that the "read-fpr&write-gpr" profile is unique, but please do go through the exercise anyway https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/pipe_data.py;hb=HEAD if later we want to reduce the number of FUs then it is possible to amortise them with some additional HDL *without* having to modify the fu/*/*.py code itself, but the other way round (separating things that have *explicitly* been merged into one fu) is *not* possible without a hell of a lot of work. madd is an example of something that also goes in its own completely separate fu because there are no other pipelines implemented yet with GPR-3-in GPR-1-out. basically "if different reg profile ==> separate FU" but that INCLUDES if the pipeline itself can CANCEL a regfile read or write. i.e. anything that is OE=1 or Rc=1 will STILL be consider "XER" and "CR" to be part of the reg profile because the *FU itself* has control over the decision whether to write (or not). i.e. don't for goodness sake separate out Rc=1 and/or OE=1 into separate FUs for the same instruction. likewise you can also see that OP_ADD takes all the "neg*" instructions because one of the operands (RB) can be an immediate, it is *STILL* the same reg profile, neg is *NOT* separated into a separate pipeline.
(In reply to Luke Kenneth Casson Leighton from comment #34) > (In reply to Jacob Lifshay from comment #31) > > should fmvtg/fcvttg be a new FU since it reads fprs and writes gprs? same > > thing with fmvfg/fcvtfg. > > ohh yes. the decision is actually made by "register profile". (when raising the new bugreport please add something similar to this: https://bugs.libre-soc.org/show_bug.cgi?id=1035#c5 then let us double-check it together before proceeding to implementation)
(In reply to Luke Kenneth Casson Leighton from comment #34) > (In reply to Jacob Lifshay from comment #31) > > (In reply to Luke Kenneth Casson Leighton from comment #30) > > > this is turning out to be a lot of work so i am increasing the budget. > > > we do have to be careful as there is supposed to be corresponding HDL > > > for them. > > > > yeah, I can implement hdl too, it shouldn't be all that complex, maybe 2-3 > > days work, > > from when you start until when you finish please keep an accurate log! will do. last time was waay more complex than this, so much harder to estimate properly. The pseudo-code basically has the entire algorithm already thought out, all I need to do is optimize from there (e.g. try to use only one shift/rotate unit). > > should fmvtg/fcvttg be a new FU since it reads fprs and writes gprs? same > > thing with fmvfg/fcvtfg. > > ohh yes. the decision is actually made by "register profile". yup, already knew that, hence why I suggested the new FUs.
working on getting fcvtfg working: https://git.libre-soc.org/?p=libreriscv.git;a=shortlog;h=e1d9f4b857993e0d237293ab507c0100ecd86c09 commit e1d9f4b857993e0d237293ab507c0100ecd86c09 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 23:37:28 2023 -0700 fix: bfp_ROUND_TO_BFP64 takes 3 arguments commit 96230fdb1d6404b7ea1ea46488e0f8fa4ec075b1 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 20:56:40 2023 -0700 fix fcvttg FPSCR.FR computation https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=304ddb4bb602b858fcbae7d349e9a50d7f515b45 commit 304ddb4bb602b858fcbae7d349e9a50d7f515b45 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 23:51:21 2023 -0700 fix fptrans unit tests' CR1 expected values since we calculate them from FPSCR now commit f9ac76bd4a8d9f3753610f6d828b9a9ecd6f6044 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 23:40:45 2023 -0700 add WIP fcvtfg unit tests commit 01dd1e10d983b5f303d75cb6348bbca4942f6c24 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 23:39:29 2023 -0700 add WIP bfp_* function commit 53449c1b4abc14ca423ece83c2a6e97f9594add1 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 23:36:15 2023 -0700 fix: bfp_ROUND_TO_BFP64 takes 3 arguments commit 981ae6fd36c3f51babf4fb86a83edeb4393e689e Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 23:35:50 2023 -0700 add more bfp_* functions commit dcbe92f180308b1205d390b165d64d3bef19fba6 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 23:32:58 2023 -0700 fix bfp_COMPARE_* when given denormal inputs commit c599550fcdb12378a8ff23468452e38fd2c66a16 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 23:28:06 2023 -0700 compute CR1 for non-compare fp Rc=1 instructions commit 9a3b737729b12565c38cb865cf85d32392e70a43 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 23:26:51 2023 -0700 support binary literals with embedded _ (e.g. 0b10_01) commit c92e1804d74b4366421839f8f7b357f2753910a7 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 20:53:23 2023 -0700 fix fcvttg FPSCR.FR computation the unit test previously assumed the rounding mode is truncate, but when I switched it to allow dynamic rounding modes, I forgot to no longer hard-code FPSCR.FR = 0 commit da5c99707775d50154a21076613393b694dca056 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 18:46:57 2023 -0700 only retrieve stack frames we need -- ~2x speed up of test_caller_fmv_fcvt commit 12a655da81a2c8b4a335b4b63ccecec01e78b7f6 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Thu May 18 18:01:08 2023 -0700 parallelize fmv/fcvt unit tests
WIP getting fcvtfg[s][.] to work commit 371d91b299c0e4bd7b23e660b9936ed40debb824 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri May 19 19:53:36 2023 -0700 must test fcvtfgs not fcvtfg for f32 test case commit 7f1aa9c9ba2415dea75e4020dc73b3fc97bbb324 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri May 19 19:52:43 2023 -0700 format code commit d595b73b068079c7392b4601b801f0a73155d372 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri May 19 19:51:39 2023 -0700 add more bfp_* functions commit eb4b86d27f608dc7b9143a4b45cd1bf26cebfff0 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri May 19 19:50:38 2023 -0700 fix bfp compare commit 0a63152ce2a45e310de149fba09bfdc94790e3ee Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri May 19 19:50:17 2023 -0700 fix typo commit 2cf7e5d4aaa5d3fc1209cbd9cd95baa47007dd75 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri May 19 19:49:12 2023 -0700 fix using python int instead of SelectableInt
https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=bd6445153bf9ad2d571fcfc84533eb5709769226 commit bd6445153bf9ad2d571fcfc84533eb5709769226 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 23 20:10:58 2023 -0700 test fcvttgo. with traps enabled commit 7145327b2fd35d35aaf2510cae6fb3ad22488811 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 23 20:10:18 2023 -0700 ISACaller: generate FP trap commit aa2ae1dcae0470f15e3a65320f68826930e43f34 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 23 19:34:15 2023 -0700 test fcvttgo. with VE=1 too commit d18a4294ce0687838133c00b4f4778c1430366b6 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 23 19:33:01 2023 -0700 fcvttg[s][o][.] needs EXTRA_UNINIT_REGS: RT commit 870f7f23273d1d0d49af9ed09d82c42f2347ef07 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 23 19:24:34 2023 -0700 add support for adding extra uninit_regs from html comment I chose an html comment since it's not part of the proposed pseudocode like so: * blah RT,RA Pseudo-code: <!-- EXTRA_UNINIT_REGS: RT --> if rand() then RT <- 42 + (RA)
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=066134b401fca5dac03a292703e805a9f87d59fa;hp=999c11ee9159222343945e3850b1e2c4a64a8623 commit 066134b401fca5dac03a292703e805a9f87d59fa Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 30 01:00:01 2023 -0700 add support for checking sprs and msr in unit tests commit 8df546fc0a12f28b3b771a81d92f6e54a7d6a654 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 30 00:50:42 2023 -0700 use a different default MSR value for unit tests since 0 isn't a very useful default
https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=28cb366e2761c46cbfaca06f1d905b36ff79bbc2 commit 28cb366e2761c46cbfaca06f1d905b36ff79bbc2 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 30 23:08:05 2023 -0700 fcvtfg works! commit 2e4dd433fcaec57a9dfbbb100c404f9a6fde77a0 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 30 23:07:08 2023 -0700 add rest of bfp* functions needed for fcvtfg commit 21ccc59afb46fd0874d28dc7b5cd8becb97e0555 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue May 30 22:08:02 2023 -0700 use raise_syntax_error for `IndentationError`s as well
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=0401e7ed1c2a94af91fcf8e6eabe3a1e0024b996 commit 0401e7ed1c2a94af91fcf8e6eabe3a1e0024b996 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Mon Jun 12 19:26:15 2023 -0700 remove fcvttgs since it's redundant https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=98a5879b14bd60964bd2676be7f261a3bd994236 commit 98a5879b14bd60964bd2676be7f261a3bd994236 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Mon Jun 12 19:25:09 2023 -0700 remove fcvttgs since it's redundant
I got fed up with tests taking so long so I did some general optimizations throughout openpower-isa.git, they sped up the test_caller_fmv_fcvt.py tests from 118s to 43s on my machine when running: pytest -n auto -v src/openpower/decoder/isa/test_caller_fmv_fcvt.py it cut down running all tests from about 5min to 3min https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=c23202498ae30addf04ab4c1e0d7262cc825cd45 full diff: https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=c23202498ae30addf04ab4c1e0d7262cc825cd45;hp=0401e7ed1c2a94af91fcf8e6eabe3a1e0024b996 commit c23202498ae30addf04ab4c1e0d7262cc825cd45 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue Jun 13 22:56:10 2023 -0700 deepcopy is really slow and unnecessary here commit 60e7c1baeffad3a1267e97bb824623ea92d4071e Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue Jun 13 22:55:49 2023 -0700 speed up StateSPRs.__init__ commit 1c356c3379b74d40786f988c9e4b1a7d707c2fca Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue Jun 13 22:55:20 2023 -0700 cache FPSCR computation since it's slow commit 14f508cb2b158244dd5098c474aa408ac6ad7dc0 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue Jun 13 22:54:28 2023 -0700 deepcopy is really slow and actually unnecessary here commit 84610562f8bb7fd9a26e1b70d5c79e120a35e2bf Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue Jun 13 22:53:52 2023 -0700 cache get_csv commit 9d3bda373229f58a6512f88787a2a589cf9cdbb9 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue Jun 13 22:53:09 2023 -0700 comment out GC collection since it's really slow and shouldn't be needed commit 3947ab6d3d2e12e94638ef11f3c4126b67ed7280 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Tue Jun 13 22:51:14 2023 -0700 cache SVP64Instruction.Prefix instance since it's slow to construct
(In reply to Jacob Lifshay from comment #43) > I got fed up with tests taking so long so I did some general optimizations > throughout openpower-isa.git, they sped up the test_caller_fmv_fcvt.py tests > from 118s to 43s on my machine awesome. profiling would show up any other opportunities
I added fmv* tests. I noticed that fmvfg[s] should not have Rc since it doesn't modify FPSCR and since fp Rc=1 just sets CR1 to bits extracted from FPSCR. I think luke would appreciate checking with him before I remove Rc=1 support, so that's what I'm doing. https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=082196180cbf33223a2bf84854831da2c2d27862
added SVP64 tests for fmv/fcvt since this tests sv.fcvttg, I'm marking fcvttg's tests done too. https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=8e74cbea8f749030a343b1e00a5b62c37611d6c9 at this point, the only thing left is to remove Rc=1 support for fmvfg*
I removed Rc=1 for fmvfg* That was that last step for this bug. https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=098a1cb5cd2af15504c122f8a722194adda29899 commit 098a1cb5cd2af15504c122f8a722194adda29899 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri Jun 16 17:52:07 2023 -0700 remove Rc=1 from fmvfg[s] commit e00438894f78f629e8d47eac661a91be7118826e Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri Jun 16 17:40:01 2023 -0700 sv_analysis: raise error instead of outputting TODO https://git.libre-soc.org/?p=libreriscv.git;a=shortlog;h=ea71ab4aa5eec741135ca1b53052e8f05fc01b2b commit ea71ab4aa5eec741135ca1b53052e8f05fc01b2b Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri Jun 16 17:53:57 2023 -0700 remove Rc=1 from fmvfg[s] commit c4ebab10499278020deb28443d78fa111452bff3 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Fri Jun 16 17:53:35 2023 -0700 misc cleanup