The fp/int moves/conversions ls006.fpintmv RFC is ready for Libre-SOC to review it, this is the last step before submitting it to the OpenPower Foundation ISA WG. https://libre-soc.org/openpower/sv/rfc/ls006.fpintmv/ Review comments should go on this bug report
i cannot yet say why/where however the style of the words has to match what is in the Power ISA spec. "just" is not one of the words. it has to be an impersonal "declarative" style, more akin to a programming language. no pronouns *at all* "Let the thing equal this". we cannot even have this: "The reader should assume x y z" because even the *implication of the existence* of another person also indirectly implies that there was a writer with which to have a relationship! so not even 3rd person is permitted. instead of "The reader should be familiar with the following documents:" it has to be "The following are pre-requisite reading for this specification" it is a very weird style, extremely rare outside of Specifications. Move a 64-bit float from a FPR to a GPR, just copying bits of the IEEE 754 representation directly. This is equivalent to stfd followed by ld. As mffpr is just copying bits, FPSCR is not affected in any way. mffpr is similar to mfvsrd, except doesn't require VSX, which is useful for SFFS implementations. * cut just * cut "As mffpr is just copying bits" (which we already know from the first sentence), a *declaration* may be made: FPSCR is unchanged. * the "similarity" sentence needs to be moved to "Observations" can i suggest copying near-verbatim the text of mfvsrd? Move a BFP32 from a FPR to a GPR, by using SINGLE to extract the standard BFP32 form from FRB and zero-extending the result to 64-bits and storing to RT. => Moves a BFP32 from a FPR to a GPR. (declaration of fact) Let FRB be converted to BFP32 form, (impersonal declaration) zero-extended to 64-bit, (programming style) and the result stored in RT. (action)
(In reply to Luke Kenneth Casson Leighton from comment #1) As mentioned in: https://bugs.libre-soc.org/show_bug.cgi?id=1015#c48 I made the changes for the GPR/FPR moves, but not yet for GPR/FPR conversions and for the description of the different kinds of FP -> Int conversions. Architecture Notes are specifically below Special Registers Altered. What do you think so far? combined diff: https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=5e573680771f7a041d93d394003d6f9f08177a98;hp=0e65eec243573c15bc0273ae86fe75df04cb2bff
as requested in: https://bugs.libre-soc.org/page.cgi?id=editcomments.html&bug_id=1068&comment_id=10697#comment_text_9 instruction aliases are up for review (though they were before then anyway, just not specifically mentioned)