Bug 1042 - OPF ISA External RFC ls009 - SVP64 svremap, svindex, svshape, svshape2
Summary: OPF ISA External RFC ls009 - SVP64 svremap, svindex, svshape, svshape2
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/openpower/sv/rf...
Depends on: 1059 1075 1043
Blocks: 1060
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Reported: 2023-03-26 19:04 BST by Luke Kenneth Casson Leighton
Modified: 2024-01-21 23:20 GMT (History)
2 users (show)

See Also:
NLnet milestone: NLnet.2022-08-051.OPF
total budget (EUR) for completion of task and all subtasks: 2500
budget (EUR) for this task, excluding subtasks' budget: 2500
parent task for budget allocation: 1009
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
[jacob] amount = 600 submitted = 2023-06-28 paid = 2023-07-12 [red] amount = 900 submitted = 2023-06-24 paid = 2023-06-28 [lkcl] amount = 1000 submitted = 2023-06-22 paid = 2023-06-25

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Comment 1 Luke Kenneth Casson Leighton 2023-03-29 10:09:23 BST 
commit 17f19a80183d260238e2cf4ba9b78ccac9fe5807 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Wed Mar 29 10:08:56 2023 +0100

    remove DCT/iDCT redundant modes which require less-efficient cos tables
    turns out that values are often repeated so why waste space especially
    when the svshape instruction is under pressure

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=17f19a80183d260238e2cf4ba9b78ccac9fe5807
Comment 2 Luke Kenneth Casson Leighton 2023-04-16 15:52:40 BST 
formally submitted this RFC on 16apr2023

commit 6af4a396069adb1725217023aa24778a7ed3e088 (HEAD -> master, origin/master, origin/HEAD)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Sun Apr 16 15:51:35 2023 +0100

    mark ls009.mdwn as onto v2
Comment 3 Jacob Lifshay 2023-04-28 09:34:22 BST 
found a spec. bug after extensive debugging while adding prefix-sum remap (#1071):
https://bugs.libre-soc.org/show_bug.cgi?id=1075
SVSTATE.SVme is LSB0 in the simulator and MSB0 in the spec

that means everyone following the spec will have the bits in the reverse order from what the simulator expects...

luke asked me to post here:
https://libre-soc.org/irclog/%23libre-soc.2023-04-28.log.html#t2023-04-28T09:31:08
Comment 4 Jacob Lifshay 2023-04-28 10:11:25 BST 
(In reply to Jacob Lifshay from comment #3)
> found a spec. bug after extensive debugging while adding prefix-sum remap
> (#1071):

in case it isn't clear from ^, we're adding parallel scan/prefix-sum remap
https://bugs.libre-soc.org/show_bug.cgi?id=1071