Bug 1048 - OPF ISA External RFC ls011 - Fixed and Floating point LD/ST-with-update EXT2xx instructions
Summary: OPF ISA External RFC ls011 - Fixed and Floating point LD/ST-with-update EXT2x...
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/openpower/sv/rf...
Depends on:
Reported: 2023-04-03 01:04 BST by Luke Kenneth Casson Leighton
Modified: 2023-09-21 10:02 BST (History)
3 users (show)

See Also:
NLnet milestone: NLnet.2022-08-051.OPF
total budget (EUR) for completion of task and all subtasks: 2500
budget (EUR) for this task, excluding subtasks' budget: 2500
parent task for budget allocation: 1009
child tasks for budget allocation:
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Description Luke Kenneth Casson Leighton 2023-04-03 01:04:24 BST

one precious bit in SVP64 LDST-Immediate is being used up as
"Post-Increment" and it has to go. more than that, there are
circumstances where Post-Increment should be used with other

thus CSV files with post-increment for ld/st and fp-l/s
need an RFC.  also needed is implementations of FP LD/ST
with postinc, the fixedpoint ones already exist.
Comment 1 Luke Kenneth Casson Leighton 2023-04-13 12:57:02 BST
commit 02dfa09233f5a6520223c0a8f30a70348f86e2f7 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Thu Apr 13 12:56:20 2023 +0100

    spotted that the Shifted-only group of LD/ST-Post-increment needs to
    be in EXT0xx but that Shifted-Post-Increment can be in EXT2xx
    i think.

needs review

Comment 3 Luke Kenneth Casson Leighton 2023-09-21 10:02:19 BST
(In reply to Luke Kenneth Casson Leighton from comment #2)
> https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;
> h=f5bf4e5891a5669311d24ebbd5ef70fb8e7791ee
> started adding english language words

shriya, nicholas, regarding this task: take a look at the above

     EA <- (RA)
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- (RA) + EXTS(D)
+Let the effective address (EA) be (RA|0).
+The byte in storage addressed by EA is loaded into
+RT[56:63]. RT[0:55] are set to 0.
+The sum (RA|0)+D is placed into register RA.
+If RA=0 or RA=RT, the instruction form is invalid.

now compare it to the words added by shriya a couple days ago:


     EA <- (RA) + EXTS(D)
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- EA
+Description:Let the effective address (EA) be the sum (RA)+ D. The
+byte in storage addressed by EA is loaded into RT 56:63.
+RT0:55 are set to 0.
+EA is placed into register RA.
+If RA=0 or RA=RT, the instruction form is invalid.
 Special Registers Altered  

(you missed out the line-breaks though, shriya - those are important.
 and also the brackets RT[0:55])

but other than that: can you see how first RA is updated **AFTER**
in one instruction (and used as the address **BEFORE** being modified)
but in the other (the one in Power ISA 3.0) it does the address
calculation (EA) *and then uses it*?

this is the task: to write the *english language* description of what
the pseudocode says.  but first we need the actual english language
itself put into the shriya_add_description branch.