https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=openpower/isa;hb=HEAD one precious bit in SVP64 LDST-Immediate is being used up as "Post-Increment" and it has to go. more than that, there are circumstances where Post-Increment should be used with other modes. thus CSV files with post-increment for ld/st and fp-l/s need an RFC. also needed is implementations of FP LD/ST with postinc, the fixedpoint ones already exist. -- * DONE: add descriptions in English to fixedload, fixedstore * DONE: add descriptions in English to fpload, fpstore * DONE: add descriptions in English to pifixedload,pifixedstore https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/pifixedload.mdwn;hb=HEAD * DONE: write pifpload, pifpstore.mdwn (copy fpload, fpstore) https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/pifpload.mdwn;hb=HEAD https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/pifpstore.mdwn;hb=HEAD * DONE: add descriptions in English to pifpload, pifpstore * DONE: add support to openpower/decoder/pseudo/pagereader.py for reading english language descriptions * DONE: include the above instructions in the ls011 RFC https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/rfc/ls011.mdwn;hb=HEAD * TODO: remove extraneous (manually-added) instructions, see comment #24 and comment #25 * TODO: re-generate and review PDF ls011.pdf * TODO: submit the RFP to the OPF ISA WG (as "radio button 2") https://openpower.foundation/isarfc/
commit 02dfa09233f5a6520223c0a8f30a70348f86e2f7 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Thu Apr 13 12:56:20 2023 +0100 spotted that the Shifted-only group of LD/ST-Post-increment needs to be in EXT0xx but that Shifted-Post-Increment can be in EXT2xx i think. needs review https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=86aad8c209609e69d6d100255afd06546c71ac1e
https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=f5bf4e5891a5669311d24ebbd5ef70fb8e7791ee started adding english language words https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=7029dab0d1647fac0834a9ee6c66e872ed2010db add actual instructions (pseudocode etc.) https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=855de96e0f9c9b7e5ac06baf22050e4580ccc9c1 add form tables
(In reply to Luke Kenneth Casson Leighton from comment #2) > https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff; > h=f5bf4e5891a5669311d24ebbd5ef70fb8e7791ee > > started adding english language words shriya, nicholas, regarding this task: take a look at the above diff. +``` EA <- (RA) RT <- ([0] * (XLEN-8)) || MEM(EA, 1) RA <- (RA) + EXTS(D) +``` + +Let the effective address (EA) be (RA|0). +The byte in storage addressed by EA is loaded into +RT[56:63]. RT[0:55] are set to 0. + +The sum (RA|0)+D is placed into register RA. + +If RA=0 or RA=RT, the instruction form is invalid. now compare it to the words added by shriya a couple days ago: https://git.libre-soc.org/?p=openpower-isa.git;a=blobdiff;f=openpower/isa/fixedload.mdwn;h=e66c461f EA <- (RA) + EXTS(D) RT <- ([0] * (XLEN-8)) || MEM(EA, 1) RA <- EA +Description:Let the effective address (EA) be the sum (RA)+ D. The +byte in storage addressed by EA is loaded into RT 56:63. +RT0:55 are set to 0. +EA is placed into register RA. +If RA=0 or RA=RT, the instruction form is invalid. + Special Registers Altered (you missed out the line-breaks though, shriya - those are important. and also the brackets RT[0:55]) but other than that: can you see how first RA is updated **AFTER** in one instruction (and used as the address **BEFORE** being modified) but in the other (the one in Power ISA 3.0) it does the address calculation (EA) *and then uses it*? this is the task: to write the *english language* description of what the pseudocode says. but first we need the actual english language itself put into the shriya_add_description branch.
1. Added English language description for lmw instruction https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=7bf0f9d543c4963dc23a3cf3413818eb2f7a90f3 2. Added English language description for ldbrx instruction https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=3421ae832b0acc3596c90b5963b7f80559c3de87 3. Added English language description for lwbrx instruction https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=5f9974443f5de178469221c8122e7b7cef39dd9f 4.Added English language description for lhbrx instruction https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=0d3fa5d08ac5c22fe4cb3bb6a893a54ad5342b64
1. Added English language description for lq instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=ed4a9ef0a17319daf421edce00737f050f7376f3 2. Added English language description for ldux instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=a15daddba7b8154832cfe26dc389fb657cbb17ec 3. Added English language description for ldu instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=a807caee952002ce79cb04f073911c0e28cc193e 4. Added English language description for ldx instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=785e0e811f1edea54508c2ef6307cc7b4b9d4160 5. Added English language description for ld instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=a0a411aef561169dfd615a4d305f7e135daf2798 6. Added English language description for lwaux instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=88e005f1dbdcc4afdb6be38ffe4667c9c9a9530a 7. Added English language description for lwax instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=ce1fdc9ad4e37e7ff0f3f10efcdb2ab2c28e2ae2 8. Added English language description for lwa instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=a3e48cfabff16242fdcdfab7ae7886186de44bf7 9. Added English language description for lwzux instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=3eb3d6b28b11e951713033ac88146c701638e135 10. Added English language description for lwzu instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=aa203af4e36e76a2238f1f073a34087ab1dfbffb 11. Added English language description for lwzx instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=104eebd225ba2a82b9e6df8df6f95448f4a7bbd4 12. Added English language description for lwz instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=99ce1c23a8f986d2cfe6aeb9ba5ccc7093a4ddde 13. Added English language description for lhax instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=f38f0c2ba22c32744af649351eb145e810ea4e0e 14. Added English language description for lha instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=5c80f045669e6f974e26524be8a146bd84c74942 15. Added English language description for lzx instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=0f28e4f9071f826b1a6598488c467c83ac537c3f 16. Added English language description for lhz instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=63940825bd335b47815005afd5944b75ab186da1 17. Added English language description for lbzx instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=3d028abd41b7c596a6b38e1329a339824a27b88c 18. Added English language description for lhaux instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=a77084011a8fef58cf80602b60cbcb1bd38d3f2f 19. Added English language description for lhau instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=cd81405250735c386a789f70d3507bc4cb02c85f 20. Added English language description for lhzux instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=c6f371ad7b115cd0b3261d750ce48ebca4360b9f 21. Added English language description for lhzu instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=d53119b479df653818fa84abffec116a1ac4fcb5 22. Added English language description for lbzu instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=486fc66860f7652c5b856c8956815587d5ef3e2d 23. Added English language description for lbzux instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=a0e6146db3f2be842eb611148405348c5c46145a 24. Added English language description for lbz instruction. https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=15b4078642cf64b58f7ed8c7207785be6e94fa9a
shriya when checking that there are no syntax errors introduced in the edits can you run this: $ python3 src/openpower/decoder/pseudo/pagereader.py > /tmp/f then quickly check the contents of /tmp/f but mainly we want to make sure that it actually runs
Okay sure.
Question: I was adding English language description for the pifixedload.mdwn file but, I cannot find the instructions- lbzup,lbzupx etc. in the PowerISA specs. Can someone help with that?
(In reply to shriya.sharma from comment #8) > Question: > I was adding English language description for the pifixedload.mdwn file but, > I cannot find the instructions- lbzup,lbzupx etc. in the PowerISA specs. Can > someone help with that? that's Nicholas's task. i would have explicitly said "work on pifixedload.mdwn". if you recall the conversations we've had, and review the (private) messages on the topic, you'll see that "pifixedload.mdwn" and "pifixedstore.mdwn" are not on the list of tasks for you, but fixedload, fixedstore, fpload and fpstore are.
(In reply to Luke Kenneth Casson Leighton from comment #9) > (In reply to shriya.sharma from comment #8) > > Question: > > I was adding English language description for the pifixedload.mdwn file but, > > I cannot find the instructions- lbzup,lbzupx etc. in the PowerISA specs. Can > > someone help with that? > > that's Nicholas's task. i would have explicitly said "work on > pifixedload.mdwn". > if you recall the conversations we've had, and review the (private) messages > on the topic, you'll see that "pifixedload.mdwn" and "pifixedstore.mdwn" are > not on the list of tasks for you, but fixedload, fixedstore, fpload and > fpstore > are. Okay, understood.
(In reply to shriya.sharma from comment #10) > Okay, > understood. awesome. (reminder: remember to trim context, just like i have done. see bug #1126 for rationale) ok so i have done this: $ git checkout shriya_add_descriptions $ git diff master and noticed immediately this: @@ -202,7 +288,17 @@ Pseudo-code: MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1] RA <- EA -Special Registers Altered: +Description: + + Let the effective address (EA) be the sum (RA)+ (RB). + RS[32:63] are stored into the word in storage addressed + by EA. + + EA is placed into register RA. + + If RA=0, the instruction form is invalid. + + Special Registers Altered: None see that "-" on "Special regs"? it means you *deleted* the critical marker indicating where "special registers" begins. you'll need to find those (there are a few) and put them back in. normally you would run the command (see comment #6) but i haven't added support for "descriptions" yet - i'll do that now. then you will get errors and you can track them down.
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=ccc34b0f9 ok very important technical term, "barfed". do a git pull in thee shriya_add_descs branch, run the command in comment #6 and you'll see how there are instructions you deleted S.R.A ok?
nicholas can you do a careful and thorough read-through of these files, comparing the english against the PDF (the file has the section numbers of the PDF we downloaded last week) and make sure that they look right? they must be literally word-for-word as well as whitespace (number of blank lines) 100% the same: no changes whatsoever. the only change is "RT-subscript-53:68" vs "RT[53:68]". everything else must be *confirmed* - with a thorough review - as being identical. https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/fixedload.mdwn;h=bcde4ec083b5afaedc3991768bf04027675c1c64;hb=1bbfcacf3fc0a6e3dd1ab64e04ae6d0961009f84
i've done the "reading" of descriptions: it is now possible to have the full details of the instruction - or almost - by creating an "outputter" which generates what should go into an RFC. little more work needed here.
shriya i have added pifpload.mdwn and pifpstore.mdwn as straight copies, so the english language can be updated, ok? https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=5b57a2a
Hello, with Luke's help i have added the English language description for lhzup.
(In reply to Nicholas_Calderwood from comment #16) > Hello, with Luke's help i have added the English language description for > lhzup. and i just did lhzupx
this is the pseudocode for pifixedstore.mdwn https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=4e81340
and for pifpload.mdwn https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=9591a0a33
I noticed that the shifted-post-increment instructions are spelled inconsistently: lbzuspx -- s before p lfdupsx -- p before s I propose we rename all instructions to be `ups` instead of `usp`. Luke, what do you think?
(In reply to Jacob Lifshay from comment #20) > I noticed that the shifted-post-increment instructions are spelled > inconsistently: oh whoops > I propose we rename all instructions to be `ups` instead of `usp`. > > Luke, what do you think? good catch. update (post-increment), shifted-indexed. yes. ups.
(In reply to Luke Kenneth Casson Leighton from comment #21) > good catch. update (post-increment), shifted-indexed. yes. ups. done and pushed to master: https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=29e7eb4329df99e6e7ade1ca30dc4514fe2f1cb4 commit 29e7eb4329df99e6e7ade1ca30dc4514fe2f1cb4 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Sun Nov 5 19:07:57 2023 -0800 rename all load/store update-shifted-post-increment to *upsx https://bugs.libre-soc.org/show_bug.cgi?id=1048#c21 https://git.libre-soc.org/?p=libreriscv.git;a=shortlog;h=d76029858415cccfbea26d3a2dd0823b89cd7859 commit d76029858415cccfbea26d3a2dd0823b89cd7859 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Sun Nov 5 19:11:05 2023 -0800 rename all other instances of ld/st *uspx -> *upsx commit fd9166f08b1f79f7aaa672ba95943ac6372fdaaf Author: Jacob Lifshay <programmerjake@gmail.com> Date: Sun Nov 5 19:05:40 2023 -0800 rename all load/store update-shifted-post-increment to *upsx https://bugs.libre-soc.org/show_bug.cgi?id=1048#c21
Luke, I added inline imports for: fixedload, fixedstore, fpload, fpstore, pifixedload, pifixedstore https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=1b25b0de237d38e761faf5d7716d0a8f3313f8f8 I noticed that some instruction entries already present in ls011.mdwn have an additional table for the instruction form. See for example lwzup, which has an D-Form table: https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/rfc/ls011.mdwn;h=9137b5d2778d420e53b79c31397ad10ed447b5ee;hb=1b25b0de237d38e761faf5d7716d0a8f3313f8f8#l377 While the inline import doesn't have the D-Form table: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/pifixedload.mdwn;h=0418b1cd4e89ec350842d373190343fcd1c72893;hb=HEAD#l171 Do the duplicate entries in ls011.mdwn need to be removed (since the inline files replace them)?
(In reply to Andrey Miroshnikov from comment #23) > Luke, I added inline imports for: > fixedload, fixedstore, fpload, fpstore, pifixedload, pifixedstore > > https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff; > h=1b25b0de237d38e761faf5d7716d0a8f3313f8f8 fanntastic. it comes out really well at the wiki page, already. hmmm should probably put some \section breaks in it somehow, or to the python "rewriter" program at least add an extra "#" in front of the sections. let me deal with that, the inline "hook" into https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/pandoc_img.py;hb=HEAD > I noticed that some instruction entries already present in ls011.mdwn have > an additional table for the instruction form. yeees. ok right, those are there for if the "Form" does not... hang on let me check what you are referring to... do you mean this: 202 ``` 203 |0 |6 |9 |10 |11 |16 |31 | 204 | PO | RT | RA| D | 205 ``` because > See for example lwzup, which has an D-Form table: > https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/rfc/ls011. > mdwn;h=9137b5d2778d420e53b79c31397ad10ed447b5ee; > hb=1b25b0de237d38e761faf5d7716d0a8f3313f8f8#l377 yes you do mean that. 372 ``` 373 |0 |6 |9 |10 |11 |16 |31 | 374 | PO | RT | RA| D | 375 ``` ok so this is *required* for the submission on what i call "radio button 3" RFC submissions, as it s R-B-3 that will *actually* go into the *actual* Power ISA spec. therefore for *RB3* they need *exactly* the same format as if you were going to go "cut/paste" from RFC into Power Spec document. this especially matters when we do entirely new instructions. but this here, what we are doing, is: 1. *not* submitting new fields (see ls004 which *does*, it adds Z23-Form and a new SH field) 2. *not* submitting R-B-3 we are submitting Radio-Button *TWO* which is simply "hey ISA WG can you please give us some general feedback on the *idea* of what we will *later* submit for actual inclusion in the Power ISA Spec" so i am not hugely concerned if the R-B-2 submission is not exactly to the letter identical to an R-B-3 submission. > While the inline import doesn't have the D-Form table: > https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/ > pifixedload.mdwn;h=0418b1cd4e89ec350842d373190343fcd1c72893;hb=HEAD#l171 sigh i know. ultimately the idea is to put those in by using Dimitry's insndb system and my pagereader.py (which reads all instructions) plugged directly into a pandoc filter: https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/rfc/Makefile;hb=HEAD 26 %.pdf: tex_out/%.mdwn ../../pandoc_img.py 27 pandoc \ 28 --pdf-engine=xelatex \ 29 -V 'mainfont:DejaVuSerif' \ 30 -V 'sansfont:DejaVuSans' \ 31 -V 'monofont:DejaVuSansMono' \ 32 -V 'mathfont:Latin Modern Math' \ 33 --filter ../../pandoc_img.py \ <- add another one basically rather than have this: 690 [[!inline pages="openpower/isa/fixedload" raw=yes ]] instead we have say... 690 <!- include-instructions(fixedload.mdwn) --> and the (TBD) pandoc filter program goes "ah HA! let me just call the insndb system and spew out a bunch of instructions in exactly Raio-Button-3 format" see how that works and is a ridiculously small amount of work for a massively effective end-result, which has the added side-bonus of *not* having us screw up by having two sets of identical instructions to maintain, *and* saves a vast amount of effort across *fifteen* RFCs? > Do the duplicate entries in ls011.mdwn need to be removed (since the inline > files replace them)? basically yes, they go. i only had them as placeholders to show the principle, maintained the summary table so as not to forget but also to have some idea of number of instructions. but the idea of literally cut/pasting 100s of instructions inline into the RFCs then hand-adding the "Form" (opcode bits/names) is an incredibly stupid one that should have been dealt with by doing a program that autogenerates what is {inline-included}, a frickin long time ago! but the rush to get RFCs in as been so intense that it just hasn't happened yet. it is what it is :)
(In reply to Luke Kenneth Casson Leighton from comment #24) > fanntastic. it comes out really well at the wiki page, already. > hmmm should probably put some \section breaks in it somehow, > or to the python "rewriter" program at least add an extra "#" > in front of the sections. > > let me deal with that, the inline "hook" into > > https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/pandoc_img.py; > hb=HEAD Yeah, I only noticed the sections not being under the top-level heading when I moved the inline import to earlier part of ls011 (see below). Didn't see any activity, and git history doesn't show changes to pandoc_img.py. I'm guessing you've been working on other tasks. > ok so this is *required* for the submission on what i call > "radio button 3" RFC submissions, as it s R-B-3 that will > *actually* go into the *actual* Power ISA spec. Ok, makes sense. For this task not needed, but in future when we get to R-B-3, it will massively reduce the documentation maintenance. > basically yes, they go. i only had them as placeholders to show the > principle, Removed the following entries from ls011.mdwn: https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=368583227251abba9ec40a1050557d1944d9feda (already present in openpower/isa/pifixedload.mdwn) - lbzup - lbzupx - lhzup - lhzupx - lhaup - lhaupx - lwzup - lwzupx - lwaupx - ldup - ldupx In addition, I've moved the inline import to the part of ls011.mdwn where these duplicate entries resided: https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=0c319b52f5e57d5dac660da37f53f3227d97ec23 I'll proceed with the removing other duplicate entries in the same way I did with the Load with Post-Update. > maintained the summary table so as not to forget but also > to have some idea of number of instructions. A note for later work: it would be useful if the instruction list (the summary list at the top of ls011) could be autogenerated. I'm guessing a pandoc py filter could be used to scan the inline markdown files. Something like detecting the following 5-line structure: ``` # [INSTRUCTION NAME] [FORM TYPE]-Form * [instruction] [args] ``` and producing an entry in the lsXX.mdwn file like this: [instruction], [rfc name], high, PO, yes, EXT2xx, no, [inline filename], 1R2W (This is just a thought that came to me now, so I didn't explore it thoroughly, and have checked how the other parameters like the "high", "PO", "EXT2xx" etc. could be deduced.) (I also seem to remember tables like this being generated during one of previous rfc submissions, just forgotten where it was.)
andrey good stuff, little busy, plugin not hugely essential, indtructions just end up each own section. no harm there.
(In reply to Andrey Miroshnikov from comment #25) > (In reply to Luke Kenneth Casson Leighton from comment #24) > > fanntastic. it comes out really well at the wiki page, already. > > hmmm should probably put some \section breaks in it somehow, > > or to the python "rewriter" program at least add an extra "#" > > in front of the sections. > > > > let me deal with that, the inline "hook" into > > > > https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/pandoc_img.py; > > hb=HEAD > Yeah, I only noticed the sections not being under the top-level heading when > I moved the inline import to earlier part of ls011 (see below). > Didn't see any activity, and git history doesn't show changes to > pandoc_img.py. > I'm guessing you've been working on other tasks. > > > ok so this is *required* for the submission on what i call > > "radio button 3" RFC submissions, as it s R-B-3 that will > > *actually* go into the *actual* Power ISA spec. > Ok, makes sense. For this task not needed, but in future when we get to > R-B-3, it will massively reduce the documentation maintenance. > > > basically yes, they go. i only had them as placeholders to show the > > principle, > Removed the following entries from ls011.mdwn: > https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff; > h=368583227251abba9ec40a1050557d1944d9feda > > (already present in openpower/isa/pifixedload.mdwn) > > - lbzup > - lbzupx > - lhzup > - lhzupx > - lhaup > - lhaupx > - lwzup > - lwzupx > - lwaupx > - ldup > - ldupx > > In addition, I've moved the inline import to the part of ls011.mdwn where > these duplicate entries resided: > https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff; > h=0c319b52f5e57d5dac660da37f53f3227d97ec23 > > > I'll proceed with the removing other duplicate entries in the same way I did > with the Load with Post-Update. > > > > maintained the summary table so as not to forget but also > > to have some idea of number of instructions. > A note for later work: it would be useful if the instruction list (the > summary list at the top of ls011) could be autogenerated. I'm guessing a > pandoc py filter could be used to scan the inline markdown files. > Something like detecting the following 5-line structure: > > ``` > # [INSTRUCTION NAME] > > [FORM TYPE]-Form > > * [instruction] [args] > ``` that's literally the definition of what pagereader.py does combined with insndb it can do exactly that > and producing an entry in the lsXX.mdwn file like this: > > [instruction], [rfc name], high, PO, yes, EXT2xx, no, [inline filename], > 1R2W yes, why do you think i was annoyed when you did those tables with 300 instructions by hand! almost all the information is autogeneratable. > (This is just a thought that came to me now, so I didn't explore it > thoroughly, and have checked how the other parameters like the "high", "PO", > "EXT2xx" etc. could be deduced.) mmm EXT2xx etc cannot be deduced realistically because it is case-by-case anlysis. > (I also seem to remember tables like this being generated during one of > previous rfc submissions, just forgotten where it was.) ls012. https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/rfc/Makefile;hb=HEAD 13 $(ls012)/areas.mdwn $(ls012)/xo_cost.mdwn \ 14 $(ls012)/level.mdwn: ls012_optable.py ls012/optable.csv 15 @echo making optables 16 --> python3 ls012_optable.py <----- 17 sigh yes optable.csv had to be done by hand... really annoying. XO could have been autogenerated though. maybe.
Removed duplicate Fixed-Point stores: stbup, stbupx, sthup, sthupx, stwup, stwupx, stdup, stdupx. https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=af645794cab13e73fa5e1f0cada344342584a00d Added FP LD Post update section (openpower/isa/fpload) https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=36c2d7f2f581809e99cd3a7a82a7f175311c3c06 Added FP ST Post update section (openpower/isa/fpstore) https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=e9f1a5fffb382515d3cb5c6d537e60f31987c8da The summary table also included the following instructions (which weren't mentioned in comment #0, but I added them for completeness): Added Fixed LD Shifted Post update section (openpower/isa/pifixedloadshift) https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=517306571ec9f1bf792118acec4100c47c73f413 Added Fixed ST Shifted Post update section (openpower/isa/pifixedstoreshift) https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=fc2a6d3269771ffeeb423b4b0d9f6928a318b5c1 Added Floating-Point LD Shifted Post update section (openpower/isa/pifploadshift) https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=bcfc69937ef94cc45e3772906a0312cf7a8c46d2 Added Floating-Point ST Shifted Post update section (openpower/isa/pifpstoreshift) https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=a175a4756f5b4e1350d2099c3f0aae4954b337ed I just noticed that "openpower/isa/fixedload" and "openpower/isa/fixedstore" define instructions already present in PowerISA 3.0/1. This means that the two inline imports for "fixedload" and "fixedstore" are not required. https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/rfc/ls011.mdwn;h=67bb26ec0f2362ce0b07372de777a9462dd69cc8;hb=a175a4756f5b4e1350d2099c3f0aae4954b337ed#l271 Should I remove them from ls011.mdwn (since nothing new is being added to the PowerISA spec)?
(In reply to Andrey Miroshnikov from comment #28) > I just noticed that "openpower/isa/fixedload" and "openpower/isa/fixedstore" > define instructions already present in PowerISA 3.0/1. yes. > This means that the two inline imports for "fixedload" and "fixedstore" are > not required. correct :) > Should I remove them from ls011.mdwn (since nothing new is being added to > the PowerISA spec)? it would be a leeetle odd (understatement) to propose instructions already added, but more than that, they are not Post-Update instructions or Shifted (or both).
(In reply to Luke Kenneth Casson Leighton from comment #29) > > This means that the two inline imports for "fixedload" and "fixedstore" are > > not required. > > correct :) Great, I removed those imports: https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=cbbefb2ef2b17dae64a459f126b42a6bd7390144 What other things need to be done before this document could be submitted via RB2? I noticed a lack of a summary and keywords. Not sure what to do for the summary. My suggested list of keywords: GPR, FPR, Move, Memory, LD/ST, Postincrement, Shifted-Postincrement
(In reply to Andrey Miroshnikov from comment #30) > Great, I removed those imports: > https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff; > h=cbbefb2ef2b17dae64a459f126b42a6bd7390144 good. > What other things need to be done before this document could be submitted > via RB2? make it look like the other RFCs basically. and sort out the TODO > I noticed a lack of a summary and keywords. Not sure what to do for the > summary. main point: without post-increment which is present in other ISAs such as 68000 and x86 it is necessary to pre-decrement outside of a loop. this is inappropriate in many scenarios. > My suggested list of keywords: > GPR, FPR, Move, Memory, LD/ST, Postincrement, Shifted-Postincrement not Move but the others are great.
(In reply to Luke Kenneth Casson Leighton from comment #31) > main point: without post-increment which is present in other ISAs > such as 68000 and x86 it is necessary to pre-decrement outside of > a loop. this is inappropriate in many scenarios. post-increment is barely present in x86, it's only in the stack-popping instructions (where they increment esp/rsp after reading) and string instructions (the non-rep-prefixed form of which are rarely used presumably because they're slow) and no where else iirc -- so not general purpose enough to be used in loops like you want, gcc and clang generate separate add/inc instructions. 68000 only has post-increment, no pre-increment. I would use arm64 as the example, since it has both post and pre-increment and is widely used. https://gcc.godbolt.org/z/j11za7Pff
(In reply to Jacob Lifshay from comment #32) > I would use arm64 as the example, since it has both post and pre-increment > and is widely used. appreciated, thanks for the important clarification. > https://gcc.godbolt.org/z/j11za7Pff