illustrating the point of why the shift-and-add instruction is beneficial is quite important, by including a table (38) LD/ST instructions. perhaps this will not be considered costly: it just depends. **prior work on ls004 is NOT part of this milestone. ONLY the addition of the LD/ST table and the associated rationale is part of this milestone*
LD/ST table added to ls004, along with a brief explanation. needs expanding https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=9ca0101bb441ed8f81b1e2f0f86538942a73d0c0 also adding to v2 of ls012, see bug #1054
missing loads: signed 8bit stbus needs to be stbsx would be nice to have but icr if part of openpower: * both sign/zero extending byte reversed loads * byte reversed fp loads/stores
(In reply to Jacob Lifshay from comment #2) > missing loads: signed 8bit > stbus needs to be stbsx do make corrections directly but do NOT add yet more instructions. > would be nice to have but icr if part of openpower: > * both sign/zero extending byte reversed loads > * byte reversed fp loads/stores in combination with post-increment this becomes almost 80 instructions which is alarming. NO MORE NEW INSTRUCTIONS. please. byterev GPR was only added for RADIX MMU support which was punished severely in BE mode.
btw jacob the strategy for this one - shift-and-add - is to include *both* shift-and-add *and* the alternatives (the LD-ST-indexed-shifted group) and let the OPF ISA WG evaluate which is better. they might actually decide LD-ST-indexed-shifted is better, we just never know. given that both ARM and x86 have them, it's not actually as hard a sell as it might sound even though it's 37 (!) instructions (excluding ld-st-indexed-shifted-postincrement) https://azeria-labs.com/memory-instructions-load-and-store-part-4/
(In reply to Luke Kenneth Casson Leighton from comment #4) > they might actually decide LD-ST-indexed-shifted is better, we just > never know. well i'm hoping they decide they want *both* shift-add and LD-ST-indexed-shifted, x86 and arm have both: https://rust.godbolt.org/z/r8azxbW8f
(In reply to Luke Kenneth Casson Leighton from comment #3) > (In reply to Jacob Lifshay from comment #2) > > missing loads: signed 8bit turns out I thought PowerISA had lba*, it doesn't...
https://git.libre-soc.org/?p=libreriscv.git;a=shortlog;h=7881bad4de0c9b5abc3fe7db2ae65181f7369bd4 commit 7881bad4de0c9b5abc3fe7db2ae65181f7369bd4 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed Apr 12 13:52:26 2023 -0700 rename typoed stbus -> stbsx commit 9a4dec12f0d7f5d47291925094f5dcb187fb965a Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed Apr 12 13:37:47 2023 -0700 shift-add is useful even with LD-ST-indexed-shifted
commit 6eeb6589a9efeb2b7b0e15972859c8445bb64302 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Thu Apr 13 03:51:33 2023 +0100 add shaddsw to optable.csv, part of ls004 actually part of ls012 (v2) bug #1051
(In reply to Luke Kenneth Casson Leighton from comment #8) > add shaddsw to optable.csv, part of ls004 > > actually part of ls012 (v2) bug #1051 fixed spelling: commit 021c3ab3a10ed8683b9bc8912ea5d08795c851e8 Author: Jacob Lifshay <programmerjake@gmail.com> Date: Wed Apr 12 19:58:07 2023 -0700 fix shaddw spelling