Created attachment 195 [details]
Diff of mw vs mw+svp64 core using yosys ls
Last Thursday I started looking into generating an external Libre-SOC core containing SVP64 (no elwidth overrides, 64-bit element width only), while also retaining Microwatt compatibility (so that we could run the same binary).
(I do apologise for not raising the bug report earlier and misusing the IRC. For anyone seeing this in the future, please see bug #1126 for how to properly report an issue.)
The core is generated from the soc repo, by calling the Makefile. I'm using the environment produced by following the ls2 setup on the wiki page.
I added a rule to the Makefile, and an argument to issuer_verilog.py, leaving all the parameters the same as 'microwatt_external_core', except setting 'svp64' to True.
When running 'make microwatt_external_core_svp64', I hit an AttributeError, with PowerDecode2 missing the signal 'use_svp64_ldst_dec'.
On Monday I looked at the commits in openpower-isa (that's where the power_decoder2.py is located). See: https://libre-soc.org/irclog/%23libre-soc.2023-07-31.log.html#t2023-07-31T13:44:10
This commit on 24th June 2021 shows the 'use_svp64_ldst_dec' signal being added): https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=847075a69e38b96376b7db0d5df0cc125da0be7a
A commit on the 12th August 2022 then removes this signal: https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=fdba782098076205d7740fc091d925d63b29a194
Using openpower-isa commit #1bbfcce929c9a1d6b1dc0fc68c84296bcc58eea1 (the one before the signal was removed), I was able to generate an external core with the SVP64 enabled.
To make sure the SVP64 related blocks are really there, I loaded the verilog file into yosys and listed the modules using ls. The diff comparing the Microwatt-compatible and MW+SVP64 is included as a text file.
Next step is to test the core within ls2.
Created attachment 196 [details]
Shows full log of ls2 synthesis
Next step was to place the generated core inside the ls2 peripheral framework and create an FPGA image.
During the yosys synthesis, I encountered many combinatorial loops, which caused the timing analysis to fail. The errors mostly occurred in dec2, specifically the sv blocks.
Full log is attached.
(In reply to Andrey Miroshnikov from comment #1)
> caused the timing analysis to fail. The errors mostly occurred in dec2,
> specifically the sv blocks.
ignore them 100%.
p.s now you know why we cannot use DDR3 and instead use HyperRAM
which can run as low as a 1 mhz clockrate.
ah: it's an error not a warning. answer: i don't know. this code was written
18+ months ago. you'll have to investigate step-by-step, first listing
actually what the loops are.
As you have suggested yesterday Luke, I tried running this mw+svp64 libre-soc core within microwatt repo's verilator, and it runs hello world!
Also started documenting the steps required to generate this core (still in progress): https://libre-soc.org/HDL_workflow/gen_core_with_svp64/
From the assembly file in hello world, I see that an instruction can be called by the machine code directly, https://git.libre-soc.org/?p=microwatt.git;a=blob;f=hello_world/head.S;h=63576063f040c707d307a6c0ea4216e16f3f2da9;hb=refs/heads/verilator_trace#l20
Now I'll need to play with pypowersim to make some svp64 machine code, which I could then insert into the hello world code and try running it.
(In reply to Andrey Miroshnikov from comment #4)
> As you have suggested yesterday Luke, I tried running this mw+svp64
> libre-soc core within microwatt repo's verilator, and it runs hello world!
hooray. so now you know, there is a bug in the version of
yosys you used to do the nextpnr-routing. verilator could
not do a simulation if there was *actually* a combinatorial loop.
> Also started documenting the steps required to generate this core (still in
> progress): https://libre-soc.org/HDL_workflow/gen_core_with_svp64/
> From the assembly file in hello world, I see that an instruction can be
> called by the machine code directly,
of course it can. that is what has been done for nearly 3 years now,
back when lauri first did the a/v mp3 work.
> Now I'll need to play with pypowersim to make some svp64 machine code, which
> I could then insert into the hello world code and try running it.
link it as a single static .o exactly as is done in media/ and you
should be done in well under 2 hours. not one month of failing because
you're not asking for guidance and think that the goal is "i have to
do this entirely by myself".
also examine konstantinos's crypto/ work as he combines assembly
functions with c functions. this is the calling convention match
up the registers declare a static header file BAM job is done.
this is all extremely straightforward been done multiple times you
just need to get on with it.