Bug 1129 - Tasks required for ls2 soc peripheral interconnect on FPGA
Summary: Tasks required for ls2 soc peripheral interconnect on FPGA
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Andrey Miroshnikov
URL:
Depends on: 1086 1127
Blocks: 1037
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Reported: 2023-08-02 19:23 BST by Andrey Miroshnikov
Modified: 2023-08-25 12:34 BST (History)
2 users (show)

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Description Andrey Miroshnikov 2023-08-02 19:23:59 BST 
As I've been looking a lot at ls2 soc peripheral interconnect, it's good to summarise the required tasks for making the ls2 simulation and fpga more usable.

* (DONE) bug #1073 - Microwatt verilator sim - setting up chroot and documentation
* (WIP) bug #1127 - Synthesise mw-svp64 core to be used in microwatt verilator or ls2 soc.
* (NOT STARTED) Run hello world with mw-svp64 core in ls2 fabric on fpga.
* (DONE) bug #1127#c4 - Run hello world with mw-svp64 core using microwatt repo verilator sim.
* (WIP) Use pypowersim to write and test basic svp64 code. Then add to hello world and run in verilator sim, and on fpga.
* (WIP) bug #1086 - Get verilator simulation of ls2 working.
* (WIP) bug #1086 - Make sure user can follow the ls2 wiki page to create full ls2 environment without manual editing (currently required due to older ls2 commit being used).
* (WIP) Check all ls2 commits after 426e2d9585cd4b1fb96a38987f97878285ee5ba7 and eventually bring ls2 wiki example up to latest commit. - This is not the highest priority, but some issues I stumbled upon were fixed later on. Thus it is important to deal with.
Comment 1 Andrey Miroshnikov 2023-08-25 12:33:21 BST 
At present, one can follow the ls2 tutorial:
https://libre-soc.org/HDL_workflow/ls2/

to synthesise a bitstream for the Arty A7-100t to run a hello world C code.

Other than this, micropython nor Linux kernel have been run (or at least documented on the wiki).