Bug 115 - SIMD ALUs needed
Summary: SIMD ALUs needed
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: ALU (including IEEE754 16/32/64-bit FPU) (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/3d_gpu/architec...
Depends on: 132 101
Blocks: 48 116
  Show dependency treegraph
 
Reported: 2019-07-25 15:37 BST by Luke Kenneth Casson Leighton
Modified: 2021-10-02 17:33 BST (History)
1 user (show)

See Also:
NLnet milestone: NLnet.2019.02.012
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation: 48
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:


Attachments

Note You need to log in before you can comment on or make changes to this bug.
Description Luke Kenneth Casson Leighton 2019-07-25 15:37:39 BST
SIMD back-end operations are needed, using the ReservationStation
infrastructure.  it would be nice to still be able to do early-out.
will need unary selection and cancellation done, first.
Comment 1 Luke Kenneth Casson Leighton 2021-10-02 17:33:13 BST
with PartitionedSignal in place, the idea here is to have a Stage API
class which automatically understands and carries the Partition Context
throughout all pipelines.

the IO Data (as defined by regspecs) is then *automatically* allocated
PartitionedSignals rather than scalar Signals and thus the ALUs, comprising
as they do of Stage API pipelines, do not need massive intrusive conversion.

a wrapper around nmigen dsl.Module can then allocate PartitionedSignals.

however this should not be "all-in", it should be dynamic runtime configureable
as to whether the ALU should be instantiated as scalar or as SIMD.