Bug 1212 - NLnet 2023 Simple-V RISC-V binutils
Summary: NLnet 2023 Simple-V RISC-V binutils
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Milestones (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/nlnet_2023_simp...
: 1198 (view as bug list)
Depends on: 905 1094 1171
Blocks: 938
  Show dependency treegraph
Reported: 2023-11-23 20:41 GMT by Luke Kenneth Casson Leighton
Modified: 2024-02-25 14:58 GMT (History)
3 users (show)

See Also:
NLnet milestone: NLnet.2023-12-121.binutils
total budget (EUR) for completion of task and all subtasks: 85000
budget (EUR) for this task, excluding subtasks' budget: 85000
parent task for budget allocation:
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:


Note You need to log in before you can comment on or make changes to this bug.
Description Luke Kenneth Casson Leighton 2023-11-23 20:41:40 GMT
Introduction (part of MOU)

This project is to enhance binutils tools to continue the autogenerated support for the RISC-V, Power and other ISAs, and to also support Simple-V Vectorisation capabilities. It will directly support the ISA Expansion project https://libre-soc.org/nlnet_2023_simplev_riscv for which a separate grant application has been made, and will build on learnings from binutils developed for POWER ISA and SVP64/Power.


Task list


# libopid: SVP64 support

libopid currently supports major parts of vanilla PPC assembly and disassembly (at least pure 32-bit instructions we currently have enumerated in openpower-isa repository). When we have everything autogenerated, it's time to make libopid support SVP64 instructions as well.

Budget: 10000
URL: https://bugs.libre-soc.org/show_bug.cgi?id=1200


# binutils: switch PPC code to libopid

binutils code base has its own implementation for PPC SVP64 extensions support. This leads to code duplication, inability to follow the specs and complicates the maintenance. Instead of code duplication, we suggest to switch to libopid, C library, once SVP64 support is completed.

Budget: 10000
URL: https://bugs.libre-soc.org/show_bug.cgi?id=1201


# insndb: RISC-V support

insndb is one of our most fundamental components regarding assembly and disassembly. However, it currently supports only PPC architecture, lacking support for RISC-V architecture.

Budget: 10000
URL: https://bugs.libre-soc.org/show_bug.cgi?id=1255


# libopid: RISC-V support

libopid is currently capable of generating the assembly/disassembly for PPC architecture. The support for RISC-V architecture must be introduced.

Budget: 10000
URL: https://bugs.libre-soc.org/show_bug.cgi?id=1256


# insndb: introduce human-readable fields format

Currently we hard-code all possible specifications and field mappings. It's difficult to manage these and keep them in sync with the documentation. We must introduce some format to generate the documentation and the code instead.

Budget: 15000
URL: https://bugs.libre-soc.org/show_bug.cgi?id=1199


# maintenance: decouple insndb and libopid

Currently insndb and libopid are parts of our openpower-isa repository. However, this is inconvenient for other projects which will rely on these tools (most notably binutils). Plus, keeping these into openpower-isa makes no sense once we support RISC-V architecture. The task is complicated by the fact that libopid and insndb make use of other openpower-isa components; each of these uses must be addressed separately.

Budget: 5000
URL: https://bugs.libre-soc.org/show_bug.cgi?id=1202


# tests: cross-check PPC Simple-V assembly between binutils and insndb

We don't have tests for binutils which check the most essential SVP64. At least assembly and disassembly as present in openpower-isa tests must be covered.

Budget: 10000
URL: https://bugs.libre-soc.org/show_bug.cgi?id=1203


# insndb: support PPC instruction aliases

insndb currently lacks support for instruction aliases. At least the instructions mentioned as aliases for vanilla PPC must be supported so that both our code and binutils can make use of it.

Budget: 5000
URL: https://bugs.libre-soc.org/show_bug.cgi?id=1140


# administrative activities

Any task includes activities related to issue tracking and monitoring. This includes not only organizing the tasks, but also providing comments to all subtasks, participating in dicussions, budget synchronization and similar activities which rather fit the main task than any of the standalone subtasks.

Budget: 5000
URL: https://bugs.libre-soc.org/show_bug.cgi?id=1257


# conferences and papers

Participation in conferences and other public events, submitting papers and articles, and other activities of that kind.

Budget: 5000
URL: https://bugs.libre-soc.org/show_bug.cgi?id=1258
Comment 1 Luke Kenneth Casson Leighton 2024-02-19 00:31:12 GMT
ok we got the "1st stage acknowledgement passing to 2nd" message, hooray.
next phase involves as usual having the full list of milestones with
budgets, remember we had these, they each need a bugreport and
budget, in comment #0 in the usual format like every other grant

* Completion of libopid (an instruction database parser)
* Completion of libopid porting of Libre-SOC infrastructure both Scalar
  Power ISA and SVP64/Power (currently based on an early iteration of
* Definition of assembler and disassembler for RISC-V instructions and
  also SVP32, 48 and 64 Vector Prefixing formats, using libopid
* Completion of definitions of Simple-V/Single formats SVP64Single,
  SVP48Single and SVP32Single and implementation support of the same
  for both Power and RISC-V
* Test vectors for libopid and binutils
* Documentation, demonstrations and Conference Papers.
Comment 2 Dmitry Selyutin 2024-02-25 14:48:04 GMT
*** Bug 1198 has been marked as a duplicate of this bug. ***
Comment 3 Dmitry Selyutin 2024-02-25 14:58:55 GMT
The preferred order and also sometimes the dependency chain:

1199 is the most critical one. Without it, we'll have to implement all the missing bits of libopid, insndb and binutils manually. I'd say it's a blocker for 1200, 1201.

1200 (libopid SVP64 support) blocks 1201 (binutils libopid migration), because binutils are to be based on libopid, but need SVP64 support there.

1201 (binutils libopid migration) blocks 1203 (binutils vs insndb tests).

Preferably insndb and libopid (and also any code it relies on) must be decoupled (1202). For binutils (1201) I'd say it's critical. We cannot force binutils clone a huge openpower-isa repository and get along with its setup. Keeping a copy of the generated code is also a bad option. Perferably the code should be "freestanding".

I'll link the task dependencies later, that's just a comment to keep this in mind.