Top-level milestone for SVP64 ISA Expansion, starting with RISC-V and
analysing VAX ARC ARM7 and Intel 486 for future work

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* Assessment of the missing RISC-V instructions (RISC-V RV64GC is only
  96 instructions whereas POWER ISA SFFS is 214) which are present in
  Power ISA 3.0 and required to enable comparable performance from
  RISC-V with Simple-V
* Implementation of the missing RISC-V instructions and instruction
  forms that makes is comparable with POWER ISA in the Scalar ISA space.
* Assessment of application of Simple-V Vector Prefixing, building on
  the work already done under NLnet Grant 2019-10-012
  <https://libre-soc.org/nlnet_2018/>
* Implementation of Simple-V in the Libre-SOC Simulator, ISACaller.
* Definition of assembler and disassembler for RISC-V instructions
  and also Simple-V in the Libre-SOC infrastructure.
* Upgrading (with the newly created instructions and forms) sv-spike
  assembler development which was prototyped previously for Simple-V 
  Specification:
  <https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv>
* Adding a comprehensive unit test base for the new instructions which
  can then be tested against sv-spike as well as ISACaller. Conversion
  of previously created instructions to the new format used in
  Libre-SOC, and adding the newly defined and created instructions.
  <https://git.libre-soc.org/?p=riscv-tests.git;a=shortlog;h=refs/heads/sv>
* Documentation, demonstrations and Conference Papers. This will include
  porting results of other completed projects (cryptoprimitives, video)
  from POWER ISA to the RISC-V/Simple-V environment
* Research and assessment of ARM7 and i486 (both on opencores.org) as
  well as ARC as to their feasibility for applying Simple-V Prefixing
  in future development projects
* Development and publication of paper in Academic Journals and
  presentation
* CI running for NLnet results
  https://bugs.libre-soc.org/show_bug.cgi?id=1235#c4
* budget-sync enhancement
    https://bugs.libre-soc.org/show_bug.cgi?id=1171
  https://libre-soc.org/irclog/%23libre-soc.2023-12-21.log.html#t2023-12-21T15:10:56