Luke wants us to base on i486, jacob disagrees (continued in comments below)
(In reply to Luke Kenneth Casson Leighton from bug #1211 comment #5) > (In reply to Jacob Lifshay from bug #1211 comment #4) > > (In reply to Luke Kenneth Casson Leighton from bug #1211 comment #0) > > > Top-level milestone for SVP64 ISA Expansion, starting with RISC-V and > > > analysing ARM7 and Intel 486 for future work > > > > I think we should focus on x86-64 since x86-32 is nearly dead at this > > point...iirc i486 support isn't even in linux anymore > > don't care. Well, I care, and NLNet probably cares, since we don't want to do work on something that basically no one will use, since the ISA is too old. We could use Intel XED: https://github.com/intelxed/xed it's an open source (Apache 2.0) x86/x86-64 instruction decoder/encoder...that looks like it should be somewhat doable to add some of SV to, and then implement a minimal simulator on top of that that runs just enough for a strcpy or something of similar complexity, that would probably be a few dozen instructions at most. this is enough for a proof-of-concept on top of an ISA (x86-64) that everyone does use. also, Intel XED has support for APX which supports 32 GPRs. > implementation exists. https://opencores.org/projects/ao486 > *assessment* not full-blown implementation. according to the readme it implements cpuid and all 486SX instructions, so basically everything but x87. so it is pretty full-blown, just not very useful for our purposes imo since basically no one will want to target a i486, it doesn't even have popcount or 64-bit atomics! if we still didn't care if anyone will use it, why not try to add SimpleV to the VAX ISA, it has a gcc target and an attempted linux port?
(In reply to Jacob Lifshay from comment #1) > Well, I care, and NLNet probably cares, since we don't want to do work on > something that basically no one will use, since the ISA is too old. reminder (four times in this bugreport already): the scope is evaluate not implement. > We could use Intel XED: > https://github.com/intelxed/xed > it's an open source (Apache 2.0) x86/x86-64 instruction > decoder/encoder...that looks like it should be somewhat doable to add some > of SV to, x86 is going to be a pain in the ass because of the hardcoded regster names. eax/ebx as a target. sigh. vectorising that is part of the evluation, but *please do not get distracted* from the deadlines by focussing on this even before the grant has been evluated, we get *no money* > and then implement a minimal simulator on top of that that runs > just enough for a strcpy or something of similar complexity, that would > probably be a few dozen instructions at most. this is enough for a > proof-of-concept on top of an ISA (x86-64) that everyone does use. scope: evaluate not implement. although xed looks real handy to do the conversion to libopid/insndb. > also, > Intel XED has support for APX which supports 32 GPRs. > > > implementation exists. https://opencores.org/projects/ao486 > > *assessment* not full-blown implementation. > > according to the readme it implements cpuid and all 486SX instructions, so > basically everything but x87. so it is pretty full-blown, exactly. and what is really nice is, if you dig a little deeper, it is a pseudocode-to-verilog compiler!! so the pseudocode is *already there* meaning that getting it into ISACaller is real simple. [... why do you think i picked it? :) ] > just not very > useful for our purposes imo since basically no one will want to target a > i486, it doesn't even have popcount or 64-bit atomics! that's ok, we can look at adding them (after finding the ones that are unpatented). idea here is to evaluate not implement although i do love the thought. i particularly want to see what the compression ratio is (bang per buck). > if we still didn't care if anyone will use it, why not try to add SimpleV to > the VAX ISA, it has a gcc target and an attempted linux port? ooo niiice! perfect! let's add it to the list...
we could also just modify bochs, which supports x86_64 and is much simpler than qemu (like risc-v's spike). it's LGPLv2+. https://github.com/bochs-emu/Bochs e.g. here's one of the subtract instructions (just 10 lines of code excluding blank lines): https://github.com/bochs-emu/Bochs/blob/4ee9d37a5f6207934003a4b4102aa3a402221bbe/bochs/cpu/arith64.cc#L222