Bug 124 - add dynamically removable/insertable pipeline registers to div pipe to allow high clock speeds
Summary: add dynamically removable/insertable pipeline registers to div pipe to allow ...
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: ALU (including IEEE754 16/32/64-bit FPU) (show other bugs)
Version: unspecified
Hardware: All All
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 116
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Reported: 2019-07-28 23:25 BST by Jacob Lifshay
Modified: 2019-07-28 23:27 BST (History)
1 user (show)

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Description Jacob Lifshay 2019-07-28 23:25:23 BST 
see second half of http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-July/002218.html