Bug 202 - potential changes to LibreSOC HDL to suit coriolis2
Summary: potential changes to LibreSOC HDL to suit coriolis2
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Hardware Layout (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on:
Blocks: 138
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Reported: 2020-03-02 17:15 GMT by Luke Kenneth Casson Leighton
Modified: 2021-10-01 15:12 BST (History)
2 users (show)

See Also:
NLnet milestone: NLNet.2019.02.029.Coriolis2
total budget (EUR) for completion of task and all subtasks: 6000
budget (EUR) for this task, excluding subtasks' budget: 6000
parent task for budget allocation: 138
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
lkcl={amount=3000, submitted=2021-04-24, paid=2021-04-24} staf={amount=3000, submitted=2021-04-21, paid=2021-04-21}


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Description Luke Kenneth Casson Leighton 2020-03-02 17:15:55 GMT
coriolis2 layout expects some specific rules regarding connections between Cells. it has sometimes been the case that only when seeing a layout is it discovered that there is a mistake or it is suboptimal. a redesign of the nmigen HDL would be needed.
Comment 1 Luke Kenneth Casson Leighton 2020-12-02 14:22:51 GMT
although it was not coriolis2 specifically we have had to change the design for SRAM (litex) because the SRAM is a fixed block.

additionally the way that pinouts work in niolib required some changes
Comment 2 Luke Kenneth Casson Leighton 2021-02-21 21:04:34 GMT
added a 4k SRAM instance over Wishbone,
involved adding "blackbox" atteibute support to coriolis2
Comment 3 Luke Kenneth Casson Leighton 2021-04-02 16:07:36 BST
verilog and ilang respect cases on names, where vhdl does not.  this is causing issues on cosimulation but also name clashes in the P&R.

Comment 4 Luke Kenneth Casson Leighton 2021-04-19 19:42:19 BST
also c4m-jtag by Staf included here, for the JTAG TAP interface, some debugging and support involved.