first most immediate things, we need some sort of wrapper-processor of the
VST files.  i renamed one (from soclayout experiments13) from memory.vst
to memory.vhdl and we have this:

ghdl -a memory.vhdl 
memory.vhdl:323:10:error: two underscores can't be consecutive
memory.vhdl:324:10:error: two underscores can't be consecutive

editing to replace the underscores we have this:

ghdl -a memory.vhdl 
memory.vhdl:1938:21:error: cannot associate in signal interface "vdd" with actual port of mode linkage

so there is quite a bit of processing which needs to be done, which i
recommend be done with an auto-parser.

Commit first setup for cocotb testing:
https://git.libre-soc.org/?p=libresoc-litex.git;a=commit;h=3e69d2095ab2e0dd64fe94ca1547ecc8a2f56719

Usage can be seen in readme file:
https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=cocotb/README.md;h=f239eccb541bf389d98fea8dac1033eb24e73ca6;hb=3e69d2095ab2e0dd64fe94ca1547ecc8a2f56719

Update by `git pull` in soc and doing `make gitupdate`; then go to
'src/soc/litex/florent/cocotb'

You also need to update c4m-jtag and `pip install modgrammar`.
modgrammar is now dependency of c4m-jtag so will be automatically installed when you (re-)install c4m-jtag.

this has shown up some naming clashes due to verilog / ilang using capital letters in netnames and vhdl being case insensitive.

https://tomverbeure.github.io/2020/11/04/VHDL_Verilog_Cosimulation_with_CXXRTL.html


https://github.com/tomverbeure/cxxrtl_eval/blob/master/blink_basic/main.cpp

https://git.libre-soc.org/?p=litex.git;a=blob;f=litex/build/sim/core/modules/jtagremote/jtagremote.c;h=87c7c159842231bba2c5e94e1e054f71c5d90e36;hb=35929c0f8a8f1cc098a6b6ebb569caca8df8c08d

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/test_jtag_tap.py;hb=HEAD

i believe it should be extremely straightforward to combine the above, this is not nmigen just cxxrtl from yosys, to create a jtag tester which speaks openocd "jtagremote" socket protocol.

at that point it will be possible to connect directly to the simulation with .svf files, from openocd commandline, as if it was a real ASIC or FPGA.

with cxxsim or more to the point yosys having both verilog and ghdl it should be possible to do pre and post pnr simulation.

https://gist.github.com/brabect1/9f8d7d144367b9f3dd77ba2a3b459f1d#file-xindep_clk-cpp-L137

this is what it would take - modifying cocotb - to allow it to
run external (c++) clocks.  neither iverilog nor verilator support
"always #period" unfortunately.

I seem to have success in iverilog with the following code:

> `timescale 1ns/1ps
> 
> module clkdrv(output reg clk);
> 
> initial begin
>     clk = 0;
>     forever begin
>         #10 clk = ~clk;
>     end
> end
> 
> endmodule

(In reply to Staf Verhaegen from comment #7)
> I seem to have success in iverilog with the following code:
> 
> > `timescale 1ns/1ps
> > 
> > module clkdrv(output reg clk);
> > 
> > initial begin
> >     clk = 0;
> >     forever begin
> >         #10 clk = ~clk;
> >     end
> > end
> > 
> > endmodule

ah good! does the wb example work? or does it hang, still?
(i will run it in a bit, am in the middle of the cxxrtl test)

ok the cxxrtl compilation of ls180, including the litex peripheral set, was successful.  took several minutes to compile.

results of running an openocd jtagremote "upload" are that the wishbone interface is not entirely functional yet.

however the DMI interface, which allows the core to be stopped, reset, and restarted, was successful.

because cxxsim can output gtkwave VCD i was able to ascertain that the core is executing at address 0x700 in a loop, which is a good sign.

investigating wishbone over jtag is the next priority.

ah ha! the error with wishbone jtag is that it is going through a converter (64 downto 32) which takes 2 cycles, and there is no "stall" signal.

consequently the stb line is dropped at the 1st of those cycles, in the middle of the conversion, because the TAP WB FSM moves from READ to READACK too early.

i will try creating a "fake" stall to stop that hspoening.

a really quick solution: set the JTAG WB Master bus data width to 32-bit wide.
this will get it to match directly with the litex bus which is also 32-bit
and the "converter" will be switched off.  this also saves gates.

the tap wb code assumed that it would be talking to a pipelined wb.  litex does not support stall and so i used that to enable "single" read/write.

wb jtag therefore now works.

the last remaining thing to do is to get the pc to reset when DMI RESET is called.

https://github.com/YosysHQ/yosys/pull/2724

cxxsim bug, but there's a workaround: use "memory" pass before
write_cxxsim.

thanks to staf for correcting sff1r_x4.vhd which had errors in it, a quick simulation of the adder test works, post BLIF.

Out of discussion on IRC here minimal clock generation block in VHDL:

    entity clkgen is port(clk: out bit);
    end entity clkgen;
    
    architecture sim of clkgen is
    signal intclk: bit := '0';
    begin
        intclk <= not intclk after 10 ns;
        clk <= intclk;
    end architecture sim;

currently doing ghdl cocotb post layout P&R using the cts.vst files.

both chip.vst / chip_r.vst and corona are a bit of a mess:

* to/from pad signals exist which have the same name as the chip in/out ports
* the names iovdd gpio iovss vdd and vss are used for both components and signals (niolib)
* gpio in niolib uses std_ulogic for the pad port but in chip/chip_r it is declared as a bit.

some of these can be corrected with post-processing, others involve renaming niolib cell components, others need the corona/chip generation to be updated.

quite a lot to do

Staf you will temporarily need this patch to blif2vst.py in alliance-check-toolkit in order to perform any kind of build:

https://gitlab.lip6.fr/vlsi-eda/coriolis/uploads/b4b17e8907b0f4a002a4d542e7f5dc2f/z7

I am currently using a script (ln_vst.sh) to link vst files:

    #!/bin/sh
    for f in *.vst; do
        n1=`basename "$f" .vst`
        n2=`awk -F " " -e '/entity/ {print $2}' "$f"`
        if [ $n1 != $n2 ]; then
            ln -s "$f" "$n2.vst"
        fi
    done

slightly messy however it is functional:

https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=blob;f=ls180/post_pnr/cocotb/test_add_boundary.py;h=b518224664cd7c2ad4a2e2672aa05aac3a012a59;hb=HEAD#l177

this test uses experiments10_verilog post-P&R vst files (*cts*), running a JTAG boundary scan.

the code is written and functions, on both pre- and post-  JTAG tests can be run successfully.  several bugs found (and fixed)