Bug 362 - improvements to nmigen and yosys
Summary: improvements to nmigen and yosys
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on: 458 364
Blocks: 175
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Reported: 2020-06-04 14:40 BST by Luke Kenneth Casson Leighton
Modified: 2021-04-10 00:57 BST (History)
1 user (show)

See Also:
NLnet milestone: NLNet.2019.10.Wishbone
total budget (EUR) for completion of task and all subtasks: 7000
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation: 175
child tasks for budget allocation: 364 458 475
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Description Luke Kenneth Casson Leighton 2020-06-04 14:40:01 BST
improvements to nmigen and yosys are needed, including CXXSim (bug #364), a
new backend for yosys that allows a 20 to 100x performance increase
in simulation speed.
Comment 1 Luke Kenneth Casson Leighton 2020-07-08 10:41:06 BST
also needed is a way for yosys (or nmigen) to optimise out constants and unused signals... *without* requiring that the entire design be flattened.

currently, coriolis2 has had to be significantly modified to cope with dangling (unused) connections.  the design is too big to flatten so it is not appropriate to call yosys flatten.

in a large OO design, module parameters can be Const or unused.  when the design RTL is flattened this is not a problem.

however without flattening yosys will *not* pass the Const parameter into the module and perform constant optimisation *in the module*, and it will *not* likewise remove unused outgoing signals *from* that module that are not externally connected to its parent.

when such non-optimised non-flattened designs are passed to coriolis2 it causes problems because of dangling (unconnected) signals.

two potential ways in which this can be fixed: in yosys, or on nmigen.
Comment 2 Luke Kenneth Casson Leighton 2021-01-13 18:42:55 GMT
see bug #458 some augmentations are needed to Value and UserValue in order to support alternative behaviour but keeping the standard nmigen API.
Comment 3 Luke Kenneth Casson Leighton 2021-04-10 00:57:27 BST
cxxsim being used in gate-level simulation, some strange segfaulting
going on, being sorted out by whitequark.  example:

https://github.com/YosysHQ/yosys/pull/2724