TODO fill out toplevel milestones for the Wishbone proposal,
ready for the MoU, add budgets for each milestone.

# Specfication Improvements
Improve the Wishbone B4 Specification to add streaming capability, comparable to AXI4-Stream, and feed the improvements back into the current stewardship for next Wishbone release.

Budget: 2.500 EUR
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=244

# Verification Models
Design Reference Implementations in nmigen and (System-)Verilog, Bus Function Models and other functionality in SystemVerilog for verification with full unit tests aiming best code coverage.

Budget: 6.500 EUR
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=245

# Formal Correctness Proofs
Design unit tests as formal proofs in nmigen which can test both nmigen and (System-)Verilog Wishbone B4 Streaming Bus Function Models.  Example peripheral (I2S Audio Streaming) to also be tested.

Budget: 2,500 EUR
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=250

# Reference Implementation / Demonstrator
Use some of the Libre RISC-V SoC peripherals as a test platform and demonstrator (I2S Audio Streaming) for the proposed standard modifications.
See https://github.com/www-asics-ws/mpac and
https://github.com/cocotb/cocotb/pull/439

Budget: 1.350 EUR
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=246


# Traveling Expenses for ORConf 2020
Traveling expenses for presenting the Wishbone improvements to the Open Hardware community once at the annual ORConf in 2020.

Budget: 650 EUR
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=248

# Additional peripherals
Seek out existing (non-streaming) Wishbone Master
and Slave Bus implementations (or implement them if necessary, or convert from AXI4 protocol), provide
formal proof unit tests of their correctness, and add additional example
peripherals.
See https://github.com/cocotb/cocotb/pull/439 in particular

Budget: 12500 EUR
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=249

# nmigen and yosys improvements
improvements to nmigen and yosys are needed, including CXXSim, a
new backend for yosys that allows a 20 to 100x performance increase
in simulation speed.

Budget: 7000 EUR
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=362

# POWER9 Core Implementation
After the decision to implement POWER9 instead of RISC-V a full from-scratch multi-issue superscalar OoO implementation of POWER9 was needed in nmigen.  This to become the later basis for adding Vectorisation, GPU and VPU instructions.

Budget: 10000 EUR
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=383

# Libre-SOC Core Documentation
The LibreSOC core is complex and comprehensive.  Its internal architecture needs to be documented in order to make its design both accessible and maintainable.

Budget: 7000 EUR
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=384