Bug 249 - Additional Wishbone B4 peripherals for Libre-SOC (including conversion from patented AXI4)
Summary: Additional Wishbone B4 peripherals for Libre-SOC (including conversion from p...
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on: 803
Blocks: 175
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Reported: 2020-03-13 15:11 GMT by Luke Kenneth Casson Leighton
Modified: 2022-10-01 03:02 BST (History)
1 user (show)

See Also:
NLnet milestone: NLNet.2019.10.043.Wishbone
total budget (EUR) for completion of task and all subtasks: 12500
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation: 175
child tasks for budget allocation: 468 795 797 801 806
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Description Luke Kenneth Casson Leighton 2020-03-13 15:11:39 GMT
Seek out existing (non-streaming) Wishbone Master
and Slave Bus implementations (or implement them if necessary, or convert from AXI4 protocol), provide
formal proof unit tests of their correctness, and add additional example
See https://github.com/cocotb/cocotb/pull/439 in particular