LS2 builds are failing to produce console output on real hardware.
After a marathon debugging session, digging into potential differences between our ppc64le server and Luke's x86 box, we've narrowed down the most likely candidate to a problem in the external UART core.
Confirming this issue is solved by uncommenting the "`define DATA_BUS_WIDTH_8" line in uart16550/rtl/verilog/uart_defines.v. A full build on the ppc64le server followed by a test on the Raptor Versa 85 board resulted in coldboot starting up and printing correct data to UART as expected.
(In reply to tpearson from comment #2) > Confirming this issue is solved by uncommenting the "`define > DATA_BUS_WIDTH_8" line in uart16550/rtl/verilog/uart_defines.v. > > A full build on the ppc64le server followed by a test on the Raptor Versa 85 > board resulted in coldboot starting up and printing correct data to UART as > expected. unnnbelievable. about frickin time that was found. microwatt "solved" this by having a local copy of the HDL. basically we need automated setup. which was always the plan, but time pressure is getting in the way. do you happen to know how to set defines *without* altering the source code? icarus verilog which is an emulator has "-D XXXX" just like in c. i don't know if that's possible with yosys or if it is possible to create a define in another file that is picked up by all .v files? (are defines global in other words)
apparently yes https://stackoverflow.com/questions/6008017/global-constant-in-verilog https://www.reddit.com/r/yosys/comments/91p4v0/how_to_define_verilog_parameters_at_synthesis/