Bug 803 - ls2/gram does not wire clock / reset controls
Summary: ls2/gram does not wire clock / reset controls
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: Other Other
: --- major
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 249 813
  Show dependency tree / graph
 
Reported: 2022-04-09 20:56 BST by tpearson
Modified: 2022-10-01 03:02 BST (History)
1 user (show)

See Also:
NLnet milestone: ---
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation:
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:

Attachments
Add an attachment (proposed patch, testcase, etc.)

Note You need to log in before you can comment on or make changes to this bug.
Description tpearson 2022-04-09 20:56:32 BST 
The current ls2/gram source trees do not wire the mandatory clock control / reset signals from the DDR PHY to the CRG.
Comment 1 Luke Kenneth Casson Leighton 2022-04-09 20:58:07 BST 
(In reply to tpearson from comment #0)
> The current ls2/gram source trees do not wire the mandatory clock control /
> reset signals from the DDR PHY to the CRG.

oink? how is anything working at all, then!
Comment 2 tpearson 2022-04-09 21:04:27 BST 
(In reply to Luke Kenneth Casson Leighton from comment #1)
> 
> oink? how is anything working at all, then!

Random chance, basically.

Fix incoming that reduces the failure mode to bistable state, and the root cause is fascinating for the remaining problems....
Comment 3 tpearson 2022-04-09 21:07:35 BST 
Fixed in GIT hashes 7cb3e51d2d2c7e1d71fc9c991697e1270f60358b (gram) and 19ed0026e91b2dd351fbd2d692fb2c6f45b42622 (ls2).

Basically, the reset system for GRAM right now is a complete mess.  You can sorta get away with it as long as all the blocks come up on the correct SCLK phase, which happens more often than you might think just from random behavior.