Bug 813 - FPGA Simulation
Summary: FPGA Simulation
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's second ASIC
Classification: Unclassified
Component: Milestones (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/HDL_workflow/ls2/
Depends on: 803 805 811 812 801 804 806
Blocks: 690 814
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Reported: 2022-04-16 18:08 BST by Luke Kenneth Casson Leighton
Modified: 2022-08-29 22:57 BST (History)
1 user (show)

See Also:
NLnet milestone: NGI.POINTER.Gigabit.ASIC
total budget (EUR) for completion of task and all subtasks: 12000
budget (EUR) for this task, excluding subtasks' budget: 12000
parent task for budget allocation: 814
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
# viola paid red={amount=12000, submitted=2022-06-20, paid=2022-07-09}

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Description Luke Kenneth Casson Leighton 2022-04-16 18:08:12 BST 
FPGA Simulation required of peripherals and core, with
basic boot

* UART16550: done, tested
* HyperRAM: done, tested
* QuadSPI: done, tested
* 10/100 Eth: added, needs further testing
* Core: done, tested
* XICS Interrupts: done, tested
* ls2 peripheral fabric: started, works great with above

https://git.libre-soc.org/?p=ls2.git;a=tree;hb=HEAD