Bug 801 - ls2/gram DDR3 controller not working on hardware
Summary: ls2/gram DDR3 controller not working on hardware
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: Other Other
: --- critical
Assignee: Luke Kenneth Casson Leighton
Depends on:
Blocks: 813
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Reported: 2022-04-07 23:22 BST by tpearson
Modified: 2022-07-07 19:33 BST (History)
1 user (show)

See Also:
NLnet milestone: NLNet.2019.10.043.Wishbone
total budget (EUR) for completion of task and all subtasks: 6000
budget (EUR) for this task, excluding subtasks' budget: 6000
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Description tpearson 2022-04-07 23:22:46 BST
On at least ECP5 hardware the ls2/gram DDR3 controller does not function.
Comment 1 tpearson 2022-04-07 23:28:09 BST
This has been traced to multiple defects in the gram HDL along with the ls2 coldboot (libgram) firmware and pin setup.

DDR3 is basically functional on the Raptor custom Versa 85 board (with some caveats, see below) as of the following commits:





memtest passes overall, but sometimes the FPGA/DDR3 PLLs/DLLs will fail to lock correctly after programming (noted as significant DQS burst detect shifts during read levelling).  This causes memtest to immediately fail with a slew of errors, but repeatedly reprogramming the same bitstream will eventually allow the DDR3 to come up again with no errors at all during either memtest or further operations.

My best guess is that the above behavior is due to a questionable DLL lock inside the DDR3 device, and is likely the result of running the device way outside of its specifications (50MHz clock vs. a minimum of 100MHz per the specifications).  Efforts to run the DDR3 device at 100MHz and the core at a lower clock frequency will be moved to a new bug report.