Bug 622 - cxxrtl bugs
Summary: cxxrtl bugs
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: Low enhancement
Assignee: whitequark
URL:
Depends on:
Blocks:
 
Reported: 2021-04-10 00:53 BST by Luke Kenneth Casson Leighton
Modified: 2021-04-10 16:41 BST (History)
1 user (show)

See Also:
NLnet milestone: ---
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation:
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:


Attachments
repro case 1 (501 bytes, application/x-wine-extension-v)
2021-04-10 00:53 BST, Luke Kenneth Casson Leighton
Details
repro case 2 (1.02 KB, application/x-wine-extension-v)
2021-04-10 00:54 BST, Luke Kenneth Casson Leighton
Details

Note You need to log in before you can comment on or make changes to this bug.
Description Luke Kenneth Casson Leighton 2021-04-10 00:53:54 BST
Created attachment 129 [details]
repro case 1

couple of bugs in cxxrtl

ERROR: Assert `cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()' failed in backends/cxxrtl/cxxrtl_backend.cc:1339.

repro cases:

    https://ftp.libre-soc.org/ls180bug2.v
    https://ftp.libre-soc.org/ls180bug.v

latest yosys master
commit a58571d0fe8971cb7d3a619a31b2c21be6d75bac (HEAD -> master, origin/master, origin/HEAD)

this is *after* the commit
#2724 from whitequark/flatten-rewrite-memwr-memid
Comment 1 Luke Kenneth Casson Leighton 2021-04-10 00:54:13 BST
Created attachment 130 [details]
repro case 2