Bug 240 - POWER-RISCV ISA switch formal standard writeup needed
Summary: POWER-RISCV ISA switch formal standard writeup needed
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Alain D D Williams
URL:
Depends on:
Blocks: 174
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Reported: 2020-03-13 12:56 GMT by Luke Kenneth Casson Leighton
Modified: 2020-12-02 15:07 GMT (History)
1 user (show)

See Also:
NLnet milestone: NLNet.2019.10.Standards
total budget (EUR) for completion of task and all subtasks: 3000
budget (EUR) for this task, excluding subtasks' budget: 3000
parent task for budget allocation: 174
child tasks for budget allocation:
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Description Luke Kenneth Casson Leighton 2020-03-13 12:56:08 GMT
A formal write-up of the means by which processors may switch to RISC-V (and back, from POWER), to be proposed to the OpenPOWER Foundation at a later date.