The vectorisation and other improvements needed for the LibreSOC need a simulator in order to test out applications at the assembly-code / binary level, prior to implementation in hardware.  An instruction-compatible simulator will be able to execute programs at reasonable speed whereas the hardware-level simulator will be hundreds of thousands of times slower.  gem5 is a suitable starting point, and the modifications to spike (RV simulator) need to be ported to it:
https://git.libre-riscv.org/?p=riscv-isa-sim.git;a=tree;h=refs/heads/sv;hb=refs/heads/sv

see this:
https://www.gem5.org/documentation/general_docs/architecture_support/