Bug 241 - OpenPOWER SImulation is needed of standards
Summary: OpenPOWER SImulation is needed of standards
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
: 256 (view as bug list)
Depends on: 232 258 581 602 618 647 665 701 728 269 272 463 604
Blocks: 174
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Reported: 2020-03-13 13:07 GMT by Luke Kenneth Casson Leighton
Modified: 2021-10-15 14:10 BST (History)
5 users (show)

See Also:
NLnet milestone: NLNet.2019.10.Standards
total budget (EUR) for completion of task and all subtasks: 12000
budget (EUR) for this task, excluding subtasks' budget: 3700
parent task for budget allocation: 174
child tasks for budget allocation: 269 272 463 588 604 647 656 705 712 728
The table of payments (in EUR) for this task; TOML format:


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Description Luke Kenneth Casson Leighton 2020-03-13 13:07:23 GMT
The vectorisation and other improvements needed for the LibreSOC need a simulator in order to test out applications at the assembly-code / binary level, prior to implementation in hardware.  An instruction-compatible simulator will be able to execute programs at reasonable speed whereas the hardware-level simulator will be hundreds of thousands of times slower.  gem5 is a suitable starting point, and the modifications to spike (RV simulator) need to be ported to it:
https://git.libre-riscv.org/?p=riscv-isa-sim.git;a=tree;h=refs/heads/sv;hb=refs/heads/sv

see this:
https://www.gem5.org/documentation/general_docs/architecture_support/
Comment 1 Luke Kenneth Casson Leighton 2020-03-13 18:29:13 GMT
*** Bug 256 has been marked as a duplicate of this bug. ***
Comment 2 Luke Kenneth Casson Leighton 2020-03-14 10:30:26 GMT
https://github.com/CSL-KU/SpectreGuard/blob/master/gem5/src/arch/power/isa/formats/integer.isa

this looks reasonable to work with.  it is a code-generator. so the hardware for-loop will go in as c code outputted as a c for-loop.
Comment 3 Luke Kenneth Casson Leighton 2020-03-14 10:31:57 GMT
https://github.com/gem5-gpu

also interesting however possibly as an aside.  however texturisation and shader functionality were added.
Comment 4 Luke Kenneth Casson Leighton 2020-03-14 14:17:34 GMT
https://github.com/cebix/macemu/blob/master/SheepShaver/src/emul_ppc/emul_ppc.cpp

another powerpc emulator
Comment 5 Luke Kenneth Casson Leighton 2020-03-14 14:18:15 GMT
http://pearpc.sourceforge.net/

another one to investigate
Comment 6 Luke Kenneth Casson Leighton 2020-03-15 16:17:04 GMT
(In reply to Luke Kenneth Casson Leighton from comment #5)
> http://pearpc.sourceforge.net/
> 
> another one to investigate

pear is, honestly, looking a lot simpler to work with, although it's going to take some unit tests like those in riscv-isa-tests to get it into shape.

see
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/005091.html

to get whatever we need into shape it will go like this:

* get "basic" (non-GUI) ability to run "bare-metal" programs.  this involves either overloading a system call (writing one), peek/poke to a memory address and having the emulator say "writes to this address are directed to stdout, reads from this address result in characters from stdin being accepted".

* start writing some *really* simple unit tests (20-50 lines of assembler) that test "addic", "mul", etc. etc.

* begin the process of allowing dynamic (runtime) emulation of 64-bit instructions (not a static emulator-compile-time option)

* *recompile* the unit tests using a 64-bit ppc compiler and test that those still work

* start adding "basic" SimpleV support (a 48-bit instruction with the 16-bit "SV" Prefix) which does *NOT* support element-width.  just a straight for-loop on integer math.

* write unit tests - in assembler - for SVPrefix add, addic, mul etc.

* move slowly forward adding full IEEE754 FP support (using Jacob's algorithmic library, so that we have *proper* POWER IEEE754 emulation, not "x86" IEEE754 rules)

* add in elwidth support, predication, and so on, basically replicate the traillazing done in the spike-sv emulator.


at the same time:

* add support for dynamic LE and BE (unit tests for the same)

* attempt to compile up more recent linux kernels, boot loaders (yaboot), in particular track down why Debian 8.0 PPC ISO cannot recognise (find) yaboot files on the ISO

* see if the MMU (TLB) code is adequate to run a 64-bit OS

* after the 64-bit bare-metal unit tests all pass, attempt to run larger programs and even a linux kernel.


we *might* also want to consider porting the spike pk library to powerpc.  it's a "bare minimum POSIX environment" which will allow the absolute bare minimum of POSIX applications to function.  or, finding something else suitable to port.
Comment 8 Luke Kenneth Casson Leighton 2020-03-16 09:59:04 GMT
thanks to hugh, he pointed me in the direction of this:
https://github.com/power-gem5

it works however it leaks memory like a sieve
Comment 9 Cole Poirier 2020-12-02 20:45:32 GMT
Revert mistaken change made to "budget (EUR) for this task, excluding subtasks' budget"
Comment 10 Luke Kenneth Casson Leighton 2021-02-11 01:13:45 GMT
(In reply to Luke Kenneth Casson Leighton from comment #8)
> thanks to hugh, he pointed me in the direction of this:
> https://github.com/power-gem5
> 
> it works however it leaks memory like a sieve

now fixed, upstream patches being submitted
Comment 11 Luke Kenneth Casson Leighton 2021-02-12 14:54:45 GMT
commit 9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Fri Feb 12 14:41:48 2021 +0000

    add srcstep and correct PC-advancing during Sub-PC looping in ISACaller

first unit test operational
Comment 12 Alain D D Williams 2021-02-12 15:43:46 GMT
BEWARE some of the API changed with version 20.1

https://www.gem5.org/project/2020/10/01/gem5-20-1.html

properties slave & master are changed to cpu_side_ports & mem_side_ports
Others also.
Comment 13 Luke Kenneth Casson Leighton 2021-02-12 16:02:47 GMT
(In reply to Alain D D Williams from comment #12)
> BEWARE some of the API changed with version 20.1
> 
> https://www.gem5.org/project/2020/10/01/gem5-20-1.html
> 
> properties slave & master are changed to cpu_side_ports & mem_side_ports
> Others also.

their mastery of the english language is second to none.  i trust that
they are not enslaved to the cult-like movement to eradicate history from
living memory.
Comment 14 Luke Kenneth Casson Leighton 2021-05-21 15:21:29 BST
command-line ISACaller
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/pypowersim.py;hb=HEAD

from Lauri:

Please have it take multiple load- and save memory options instead of
just one blob.

--load file1 0x100 --load file2 0x500 --save out1 0x100 0x100 --save
out2 0x500 0x100

- Lauri
Comment 15 Luke Kenneth Casson Leighton 2021-07-01 11:36:11 BST
https://github.com/phaa-eu/cavatools/tree/main/caveat

a multi-process high speed simulator
Comment 16 Jacob Lifshay 2021-08-25 18:12:43 BST
forgot to account for budget assigned to bug #656
Comment 17 Luke Kenneth Casson Leighton 2021-09-19 18:26:14 BST