FP Load, Store and arithmetic operations are needed in the ISACaller simulator * fadds DONE test DONE * fcfids TODO test DONE execpt FPSCR, moved to bug #705 * fmuls DONE test DONE * fneg DONE test DONE * fsubs DONE test DONE * lfd DONE test TODO * lfiwax DONE test TODO * lfs DONE test DONE * lfsu DONE test DONE * lfsx DONE test DONE * stfd DONE test TODO * stfs DONE test DONE * stfsu DONE test DONE * stfsx DONE test DONE * stfsux DONE test DONE FPSCR needed here https://libre-soc.org/openpower/isafunctions/fpfromint/
i've (already) added the pseudo-code for FP Load, there's no infrastructure in place for it, it's just the first step. FP Store is next, basic FP ops after that.
commit 4ce0c861739bdc8062b20da98315eecc1144a2bd (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Fri May 14 17:13:09 2021 +0100 add zero-variant (RA|0) in fpload pseudocode, cleaner, clearer commit d8ea5bee68f04dec225bcc4dfe2179118c81c799 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Fri May 14 17:11:42 2021 +0100 add fpstore.mdwn commit a0e4e3494219dab44bbcc5fd7627dc9a72cd69b3 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Fri May 14 16:49:24 2021 +0100 add fpload.mdwn for FP simulation
commit dc73af22ffcd11b30eefd18c85a18deb5455b2d8 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Fri May 14 20:13:06 2021 +0100 add FPR (FP Regfile) to ISACaller commit d361a9a07804e1eb0e78138c582541cfa80d7292 (origin/master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Fri May 14 20:07:00 2021 +0100 add in FPR.getz and support for FPR(x) in ISA parser commit 599b613a22d1339a20007c719230a574a90b0195 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Fri May 14 18:59:20 2021 +0100 add fpmove.mdwn from v3.0B p150 book I section 4.6.5
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=eb160da0b7805cd782eed94dc4b99fe6e48f74b0 first FP instruction and unit test added, with single to double conversion: lfsx
major 35 => (LDST, NONE, OP_LOAD, RA_OR_ZERO, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', DUPD), -- lbzu 50 => (LDST, FPU, OP_LOAD, RA_OR_ZERO, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- lfd 51 => (LDST, FPU, OP_LOAD, RA_OR_ZERO, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', DUPD), -- lfdu 48 => (LDST, FPU, OP_LOAD, RA_OR_ZERO, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', NONE), -- lfs 49 => (LDST, FPU, OP_LOAD, RA_OR_ZERO, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0', DUPD), -- lfsu 54 => (LDST, FPU, OP_STORE, RA_OR_ZERO, CONST_SI, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- stfd 55 => (LDST, FPU, OP_STORE, RA_OR_ZERO, CONST_SI, FRS, RA, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', NONE), -- stfdu 52 => (LDST, FPU, OP_STORE, RA_OR_ZERO, CONST_SI, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', NONE), -- stfs 53 => (LDST, FPU, OP_STORE, RA_OR_ZERO, CONST_SI, FRS, RA, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0', NONE), -- stfsu minor 31 2#1001010111# => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- lfdx 2#1001110111# => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', DUPD), -- lfdux 2#1101010111# => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', NONE), -- lfiwax 2#1101110111# => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- lfiwzx 2#1000010111# => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', NONE), -- lfsx 2#1000110111# => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0', DUPD), -- lfsux 2#1011010111# => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- stfdx 2#1011110111# => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, FRS, RA, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', NONE), -- stfdux 2#1111010111# => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- stfiwx 2#1010010111# => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', NONE), -- stfsx 2#1010110111# => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, FRS, RA, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0', NONE), -- stfsux
commit e89771fc4c865fd8d6a26ca54b577dbc17397126 (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Sat May 15 12:29:46 2021 +0100 add load/store FP indexed instructions to minor_31.csv
commit 22be40bce67738a2feab9e42bfda12e3f902e5a5 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Sat May 15 12:40:05 2021 +0100 add FP LD/ST D-Form operations to major.csv
commit ad001e8738472553964a28e2f064e0b5f07809f7 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Sat May 15 17:41:52 2021 +0100 add fabs unit test commit 56cffc2aecafe55017990a9a26e7ffdcfb255b5f (origin/master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Sat May 15 17:38:03 2021 +0100 add fp mv test, correct pseudocode
commit cb71f8342883992ee51f54275d4cee897a4f1745 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Sat May 15 20:09:54 2021 +0100 FP mul test, correct pseudocode to use FRC
fcfids needs A.3 pseudocode The conversion is described fully in Section A.3, “Float- ing-Point Convert from Integer Model”. https://libre-soc.org/openpower/isafunctions/fpfromint/
(In reply to Luke Kenneth Casson Leighton from comment #10) > fcfids needs A.3 pseudocode > > The conversion is described fully in Section A.3, “Float- ing-Point Convert > from Integer Model”. > > https://libre-soc.org/openpower/isafunctions/fpfromint/ done initial version, unit test with some simple numbers (7, -31) are functional. https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=1783b84047d5efcc04b90bfe040fa516f5e0be5f
commit 32a18d1d8220923ee84d1b2c1b78b651c33e9715 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Thu Sep 23 14:59:52 2021 +0100 add fsubs unit test
commit e0641eb5dea0ba6c5cc7f196201edd040f99c52a (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Thu Sep 23 15:05:12 2021 +0100 add load-immediate unit test
commit a432dafa65df71b83a7bbf8ee466b69e0742785e (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Thu Sep 23 15:21:38 2021 +0100 add stfsux and unit test, code was there, needed adding to power_enums
commit 52721e139617bc7b75125daf4ee0c5249f743f41 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Thu Sep 23 15:25:10 2021 +0100 add stfx unit test
commit 79a0b556aa5009749eaca95a4cb17c17673ad273 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Thu Sep 23 15:27:54 2021 +0100 add stfs unit test