Bug 618 - add SVP64 predication to ISACaller
Summary: add SVP64 predication to ISACaller
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/openpower/sv/im...
Depends on:
Blocks: 241
  Show dependency tree / graph
 
Reported: 2021-03-17 15:21 GMT by Luke Kenneth Casson Leighton
Modified: 2021-03-17 20:42 GMT (History)
1 user (show)

See Also:
NLnet milestone: ---
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation:
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:

Attachments
Add an attachment (proposed patch, testcase, etc.)

Note You need to log in before you can comment on or make changes to this bug.
Description Luke Kenneth Casson Leighton 2021-03-17 15:21:57 GMT 
both single and twin predication needs adding to ISACaller simulator,
for CR and INT sources.

* INT-based single: done
* CR-based single:  done
* INT-based twin:   TODO
* CR-based twin:    TODO
* Zeroing single:   TODO
* Zeroing twin:     TODO
Comment 1 Luke Kenneth Casson Leighton 2021-03-17 15:23:08 GMT 
commit 379cc6df93eec26dae0fc523b18a1996f1e90d97 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Wed Mar 17 15:20:02 2021 +0000

    add SVP64 INT-style predication to ISACaller
Comment 2 Luke Kenneth Casson Leighton 2021-03-17 20:42:53 GMT 
commit 4a62e46f76219b3c02fee379047d8a18df2f22fc (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Wed Mar 17 20:40:49 2021 +0000

    add CR-based predication to ISACaller