https://libre-soc.org/irclog/%23libre-soc.2021-12-17.log.html#t2021-12-17T23:26:38 pypowersim is not documented, and needs some explanation / tutorial on how to set it up, load registers, output memory sections afterwards etc.
andrey do you want this one? there's these: https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/test/basic_pypowersim;hb=HEAD https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/test/basic_pypowersim_fp;hb=HEAD https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=media/audio/mp3/mp3_0.sh;hb=HEAD which at a certain level are self-explanatory but a quick page (URL above) would be handy (and justify EUR 800)
(In reply to Luke Kenneth Casson Leighton from comment #1) > andrey do you want this one? there's these: Sure, just need to understand what it does and what it's for. > > https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/test/ > basic_pypowersim;hb=HEAD This is what I get when I run make: Traceback (most recent call last): File "/usr/local/bin/pypowersim", line 11, in <module> load_entry_point('libresoc-openpower-isa', 'console_scripts', 'pypowersim')() File "/home/rohdo/src/openpower-isa/src/openpower/decoder/isa/pypowersim.py", line 332, in run_simulation mem = read_data(fname, offs) File "/home/rohdo/src/openpower-isa/src/openpower/decoder/isa/pypowersim.py", line 28, in read_data res[offset] = struct.unpack('<Q', b)[0] # unsigned long struct.error: unpack requires a buffer of 8 bytes make: *** [Makefile:11: sim] Error 1 > https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/test/ > basic_pypowersim_fp;hb=HEAD Traceback (most recent call last): File "/usr/local/bin/pypowersim", line 11, in <module> load_entry_point('libresoc-openpower-isa', 'console_scripts', 'pypowersim')() File "/home/rohdo/src/openpower-isa/src/openpower/decoder/isa/pypowersim.py", line 366, in run_simulation initial_pc=initial_pc) File "/home/rohdo/src/openpower-isa/src/openpower/decoder/isa/pypowersim.py", line 149, in run_tst initial_regs=initial_regs, initial_fprs=initial_fprs) File "/home/rohdo/src/openpower-isa/src/openpower/simulator/qemu.py", line 261, in run_program q = QemuController(program.binfile, bigendian) File "/home/rohdo/src/openpower-isa/src/openpower/simulator/qemu.py", line 50, in __init__ self.gdb = GdbController(gdb_path='powerpc64-linux-gnu-gdb') TypeError: __init__() got an unexpected keyword argument 'gdb_path' make: *** [Makefile:10: sim] Error 1 > https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=media/audio/mp3/ > mp3_0.sh;hb=HEAD Traceback (most recent call last): File "/usr/local/bin/pypowersim", line 11, in <module> load_entry_point('libresoc-openpower-isa', 'console_scripts', 'pypowersim')() File "/home/rohdo/src/openpower-isa/src/openpower/decoder/isa/pypowersim.py", line 319, in run_simulation initial_regs = read_entries(arg, 128) File "/home/rohdo/src/openpower-isa/src/openpower/decoder/isa/pypowersim.py", line 67, in read_entries with open(fname) as f: FileNotFoundError: [Errno 2] No such file or directory: 'audio/mp3/mp3_0.gpr'
(In reply to Andrey Miroshnikov from comment #2) > self.gdb = GdbController(gdb_path='powerpc64-linux-gnu-gdb') > TypeError: __init__() got an unexpected keyword argument 'gdb_path' > make: *** [Makefile:10: sim] Error 1 you've the wrong version of pygdbmi, check setup.py > FileNotFoundError: [Errno 2] No such file or directory: 'audio/mp3/mp3_0.gpr' you ran from the wrong directory. look at the directory structure to deduce the correct location
see https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=media/README.txt;hb=HEAD then inspect the Makefile 40 @echo audio/mp3_0 41 for i in `seq 0 1000 9000`; do \ 42 audio/mp3/mp3_0.sh $$i $$DUMP$$i || exit 1; \ so you'll need to do: $ make wget $ ./audio/mp3/mp3_0.sh 0 out0
https://libre-soc.org/irclog/%23libre-soc.2022-06-28.log.html#t2022-06-28T15:57:15
Updated the wiki page, have a look if this is sufficient: https://libre-soc.org/docs/pypowersim/
(In reply to Andrey Miroshnikov from comment #6) > Updated the wiki page, have a look if this is sufficient: > https://libre-soc.org/docs/pypowersim/ notes look good for an overview, note that it doesn't "run SV", it is an *actual* Power ISA simulator, which happens to have had support for SV added to it. this becomes relevant, below. now let's go onto an actual program. https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/test/basic_pypowersim/Makefile;hb=HEAD https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/test/basic_pypowersim/test.s;hb=HEAD note that test.s has absolutely no SVP64 instructions in it whatsoever? 3 lis 2, 0x2000 4 ori 2, 2, 0x0100 this is loading the constant 0x2000_0100 into r2. which is then used in the next two instructions: 5 std 1, 0(2) 6 lhz 1, 4(2) and, surpriiise! back in Makefile: 14 --dump testout2.bin:0x20000100:8 \ 8 bytes at memory location 0x2000_0100 are "dumped" into testout2.bin and are found to contain 0xdeadbeef 1 lis 1, 0xdead # test comment 2 ori 1, 1, 0xbeef which was exactly what was put into r1. so again there's a trail there. it's an *actual* Power ISA simulator. it's not "an executor of SV assembler". Assembler code written in SV is this is wrong. it's a *binary* Power ISA simulator. pysvp64asm happens to be a temporary solution to insert SVP64 assembler (Dmitry's working on binutils gas to actually add SVP64 support)
(In reply to Luke Kenneth Casson Leighton from comment #7) > notes look good for an overview, note that it doesn't "run SV", it is > an *actual* Power ISA simulator, which happens to have had support for > SV added to it. this becomes relevant, below. Thanks for the clarification, fixed my description. https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=ccbd54ccd0e87b6b204e9088eb19bae87dd7cac7 I'll continue looking into pypowersim and try to expand the wiki.
+PowerISA assembler code is decoded by a given ISA class instance Power ISA *binaries* are decoded then perhaps a second sentence, SVP64 binaries are also supported.
happy with how this page looks.
andrey do make sure to run budget-sync to check the format of the fields is correct