Bug 308 - POWER variable-length encoding scheme needed
Summary: POWER variable-length encoding scheme needed
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks:
 
Reported: 2020-05-13 10:37 BST by Luke Kenneth Casson Leighton
Modified: 2020-09-21 03:47 BST (History)
2 users (show)

See Also:
NLnet milestone: NLNet.2019.10.046.Standards
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation: 174
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:

Attachments
Add an attachment (proposed patch, testcase, etc.)

Note You need to log in before you can comment on or make changes to this bug.
Description Luke Kenneth Casson Leighton 2020-05-13 10:37:52 BST 
instruction stream order needs to be sorted out so that the proposed
Compressed/48/64/VBLOCK encoding will fit.  currently, LE on POWER
is wholly unsuited to variable-length ISA encoding due to the opcode
being at the wrong end of a sequential instruction byte stream

https://libre-soc.org/openpower/

http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006553.html
Comment 1 Luke Kenneth Casson Leighton 2020-05-13 10:38:44 BST 
note, not to be confused with bug #238 which is *actual* compressed
(16-bit) instruction encodings.