Bug 330 - create POWER9 Logic Pipeline
Summary: create POWER9 Logic Pipeline
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Mac OS
: --- enhancement
Assignee: Michael Nolan
URL:
Depends on: 356 361 331 360
Blocks: 383
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Reported: 2020-05-20 16:19 BST by Luke Kenneth Casson Leighton
Modified: 2021-04-24 18:18 BST (History)
2 users (show)

See Also:
NLnet milestone: NLNet.2019.10.Wishbone
total budget (EUR) for completion of task and all subtasks: 300
budget (EUR) for this task, excluding subtasks' budget: 300
parent task for budget allocation: 383
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
"lkcl"={amount=150, paid=2020-08-21} "donated"={amount=150, submitted=2021-04-24}


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Description Luke Kenneth Casson Leighton 2020-05-20 16:19:34 BST
a pipeline is needed implementing POWER9 logical operations

* https://libre-soc.org/openpower/isa/fixedlogical/
* https://git.libre-soc.org/?p=soc.git;a=tree;f=src/soc/fu/logical;hb=HEAD
Comment 1 Luke Kenneth Casson Leighton 2020-05-21 01:57:26 BST
i'm not seeing anything in main_stage.py that uses XER carry_in.  it appears extraneous.  sticky overflow on the other hand, because carry can be generated, should be.
Comment 2 Luke Kenneth Casson Leighton 2020-05-22 18:17:57 BST
michael i am just reviewing the isatables for LOGICAL operations.  two things struck me:

1. CR0 is apparently an input for OP_CNTZ but not an output, and we have no cr0 in LogicalInputData.

2. i am not seeing any of the LOGICAL operations listed as needing carry in nor producing carry out.

looking here:
https://libre-soc.org/openpower/isa/fixedlogical/

it does not appear that any or them set anything other than CR0 and that is an output only.
Comment 3 Michael Nolan 2020-05-22 19:30:50 BST
(In reply to Luke Kenneth Casson Leighton from comment #2)
> michael i am just reviewing the isatables for LOGICAL operations.  two
> things struck me:
> 
> 1. CR0 is apparently an input for OP_CNTZ but not an output, and we have no
> cr0 in LogicalInputData.

That's a mistake, fixing...

> 
> 2. i am not seeing any of the LOGICAL operations listed as needing carry in
> nor producing carry out.
> 
> looking here:
> https://libre-soc.org/openpower/isa/fixedlogical/
> 
> it does not appear that any or them set anything other than CR0 and that is
> an output only.

They shouldn't need carry no. 

BTW, did the logical pipe's output stage get replaced with common_output_stage? The logical pipe test is broken and I'm not sure how to fix it.
Comment 4 Luke Kenneth Casson Leighton 2020-05-22 19:38:07 BST
(In reply to Michael Nolan from comment #3)
> (In reply to Luke Kenneth Casson Leighton from comment #2)
> > michael i am just reviewing the isatables for LOGICAL operations.  two
> > things struck me:
> > 
> > 1. CR0 is apparently an input for OP_CNTZ but not an output, and we have no
> > cr0 in LogicalInputData.
> 
> That's a mistake, fixing...

ok excellent.  it didn't show up in the unit tests.

> > 
> > 2. i am not seeing any of the LOGICAL operations listed as needing carry in
> > nor producing carry out.
> > 
> > looking here:
> > https://libre-soc.org/openpower/isa/fixedlogical/
> > 
> > it does not appear that any or them set anything other than CR0 and that is
> > an output only.
> 
> They shouldn't need carry no. 

ok good to confirm.
 
> BTW, did the logical pipe's output stage get replaced with
> common_output_stage?

yes and common_input_stage as well.

> The logical pipe test is broken and I'm not sure how to
> fix it.

you might have been in between git pulls, can you try again?