Bug 360 - move RS to 1st or 2nd operand in CSV files
Summary: move RS to 1st or 2nd operand in CSV files
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Mac OS
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on:
Blocks: 305 314 330 339
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Reported: 2020-06-01 13:39 BST by Luke Kenneth Casson Leighton
Modified: 2020-06-30 16:43 BST (History)
1 user (show)

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Description Luke Kenneth Casson Leighton 2020-06-01 13:39:35 BST
we are doing this - a lot - i.e. in nearly every single Function Unit:

        # RA (or RC)
        reg3_ok = yield dec2.e.read_reg3.ok
        reg1_ok = yield dec2.e.read_reg1.ok
        assert reg3_ok != reg1_ok
        if reg3_ok:
            data1 = yield dec2.e.read_reg3.data
            res['a'] = sim.gpr(data1).value
        elif reg1_ok:
            data1 = yield dec2.e.read_reg1.data
            res['a'] = sim.gpr(data1).value

if instead the CSV files *specified* that RS was in position (read_reg1)
*already*, this would no longer be necessary.

the same thing applies to ShiftRot - except this time RS and RB should
be actually *swapped over*.

this is quite a big change as it affects every single Function Unit,
unit test, and formal proof.
Comment 1 Luke Kenneth Casson Leighton 2020-06-01 22:41:59 BST
turns out we can't do this for SHIFT_ROT but it can be done for:

* CR (for MTCRF)
* ALU (for EXTS)
* Logical (for a bunch of stuff)
Comment 2 Luke Kenneth Casson Leighton 2020-06-07 16:08:16 BST
MUL and DIV pipelines also need checking: however these actually have
3-operand RA RB RC so it *may* not be applicable.