we are doing this - a lot - i.e. in nearly every single Function Unit: # RA (or RC) reg3_ok = yield dec2.e.read_reg3.ok reg1_ok = yield dec2.e.read_reg1.ok assert reg3_ok != reg1_ok if reg3_ok: data1 = yield dec2.e.read_reg3.data res['a'] = sim.gpr(data1).value elif reg1_ok: data1 = yield dec2.e.read_reg1.data res['a'] = sim.gpr(data1).value if instead the CSV files *specified* that RS was in position (read_reg1) *already*, this would no longer be necessary. the same thing applies to ShiftRot - except this time RS and RB should be actually *swapped over*. this is quite a big change as it affects every single Function Unit, unit test, and formal proof.
turns out we can't do this for SHIFT_ROT but it can be done for: * CR (for MTCRF) * ALU (for EXTS) * Logical (for a bunch of stuff)
MUL and DIV pipelines also need checking: however these actually have 3-operand RA RB RC so it *may* not be applicable.