Bug 435 - PC and MSR need to be in the "state" (Decode2Execute1Type)
Summary: PC and MSR need to be in the "state" (Decode2Execute1Type)
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on:
Blocks: 335 383
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Reported: 2020-07-21 14:14 BST by Luke Kenneth Casson Leighton
Modified: 2020-12-02 20:45 GMT (History)
1 user (show)

See Also:
NLnet milestone: NLNet.2019.10.043.Wishbone
total budget (EUR) for completion of task and all subtasks: 100
budget (EUR) for this task, excluding subtasks' budget: 100
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Description Luke Kenneth Casson Leighton 2020-07-21 14:14:51 BST
to save on regfile ports, PC and MSR need to be pased in to
PowerDecode2 (MSR already is), and put into Decode2Execute1Type
then copied into XXX_input_record (CompXXXOpSubset) as appropriate.

this affects branch, trap and spr pipelines.