Bug 348 - POWER9 SPR pipeline needed
Summary: POWER9 SPR pipeline needed
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Mac OS
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
: 315 (view as bug list)
Depends on: 356 418 481 344
Blocks: 383
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Reported: 2020-05-24 22:46 BST by Luke Kenneth Casson Leighton
Modified: 2020-12-14 19:31 GMT (History)
2 users (show)

See Also:
NLnet milestone: NLNet.2019.10.Wishbone
total budget (EUR) for completion of task and all subtasks: 300
budget (EUR) for this task, excluding subtasks' budget: 300
parent task for budget allocation: 383
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
"lkcl"={amount=250,submitted=2020-12-06} jacob={amount=50,paid=2020-12-09}


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Description Luke Kenneth Casson Leighton 2020-05-24 22:46:58 BST
OP_MTSPR, OP_MFSPR operations to be added to an SPR pipeline.

with some of the SPRs being in a separate regfile (XER, LR, CTR, SRR1, SRR2)
this pipeline is slightly more involved than it seems.   it also requires
quite a lot of regfile ports.

inputs and outputs:

* FAST regfile - LR/CTR/SRR1/SRR2  done
- XER regfile                      done
* SLO sprfile - all other SPRs     done
* INT regfile                      done
* tb, dec                          done

see https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl
https://libre-soc.org/openpower/isa/sprset/

* OP_MTSPR - done, test needed, SPR slow done
* OP_MFSPR - done, test needed, SPR slow done

note that setb is not implemented by microwatt

source:

https://git.libre-soc.org/?p=soc.git;a=tree;f=src/soc/fu/spr;hb=HEAD
Comment 1 Luke Kenneth Casson Leighton 2020-05-24 22:49:44 BST
OP_MFSPR - note that XER is "constructed"

report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
    "=" & to_hstring(a_in);
if is_fast_spr(e_in.read_reg1) then
    result := a_in;
    if decode_spr_num(e_in.insn) = SPR_XER then
	-- bits 0:31 and 35:43 are treated as reserved and return 0s
        -- when read using mfxer
	result(63 downto 32) := (others => '0');
	result(63-32) := v.e.xerc.so;
	result(63-33) := v.e.xerc.ov;
	result(63-34) := v.e.xerc.ca;
	result(63-35 downto 63-43) := "000000000";
	result(63-44) := v.e.xerc.ov32;
	result(63-45) := v.e.xerc.ca32;
else
    case decode_spr_num(e_in.insn) is
    when SPR_TB =>		result := ctrl.tb;
    when SPR_DEC =>		result := ctrl.dec;
    when others =>		result := (others => '0');
    end case;
Comment 2 Luke Kenneth Casson Leighton 2020-05-27 15:57:34 BST
OP_MTSPR:

if is_fast_spr(e_in.write_reg) then
    result := c_in;
    result_en := '1';
    if decode_spr_num(e_in.insn) = SPR_XER then
	v.e.xerc.so := c_in(63-32);
	v.e.xerc.ov := c_in(63-33);
	v.e.xerc.ca := c_in(63-34);
	v.e.xerc.ov32 := c_in(63-44);
	v.e.xerc.ca32 := c_in(63-45);
	v.e.write_xerc_enable := '1';
else
    -- slow spr
    case decode_spr_num(e_in.insn) is
    when SPR_DEC =>
	ctrl_tmp.dec <= c_in;
    when others =>
        -- mtspr to unimplemented SPRs should be a nop in
        -- supervisor mode and a program interrupt for user mode
        if ctrl.msr(MSR_PR) = '1' then
              illegal := '1';
    end case;
Comment 3 Jacob Lifshay 2020-05-27 18:40:44 BST
(In reply to Luke Kenneth Casson Leighton from comment #1)
>     if decode_spr_num(e_in.insn) = SPR_XER then
> 	-- bits 0:31 and 35:43 are treated as reserved and return 0s
>         -- when read using mfxer

from what I recall, at least some of the reserved XER bits are software writable and need to be implemented.
Comment 4 Luke Kenneth Casson Leighton 2020-05-27 18:58:34 BST
(In reply to Jacob Lifshay from comment #3)
> (In reply to Luke Kenneth Casson Leighton from comment #1)
> >     if decode_spr_num(e_in.insn) = SPR_XER then
> > 	-- bits 0:31 and 35:43 are treated as reserved and return 0s
> >         -- when read using mfxer
> 
> from what I recall, at least some of the reserved XER bits are software
> writable and need to be implemented.

can you recall where and drop the relevant text and ref here?  technically it is possible to shadow the bits from the slow SPR regfile but it is messy.
Comment 5 Jacob Lifshay 2020-05-28 17:20:15 BST
(In reply to Luke Kenneth Casson Leighton from comment #4)
> (In reply to Jacob Lifshay from comment #3)
> > (In reply to Luke Kenneth Casson Leighton from comment #1)
> > >     if decode_spr_num(e_in.insn) = SPR_XER then
> > > 	-- bits 0:31 and 35:43 are treated as reserved and return 0s
> > >         -- when read using mfxer
> > 
> > from what I recall, at least some of the reserved XER bits are software
> > writable and need to be implemented.
> 
> can you recall where and drop the relevant text and ref here?  technically
> it is possible to shadow the bits from the slow SPR regfile but it is messy.

it's in section
3.2.2 Fixed-Point Exception Register page 50 (74 of PDF)
of Power ISA v3.1
<describing XER bit fields>
46:56 Reserved
Bits 48:55 are implemented, and can be read
and written by software as if the bits contained
a defined field.
57:63 This field specifies the number of bytes to be
transferred by a Load String Indexed or Store
String Indexed instruction.

Bits 48:55 of the XER correspond to bits 16:23 of
the XER in the POWER Architecture. In the
POWER Architecture bits 16:23 of the XER contain
the comparison byte for the lscbx instruction.
Power ISA lacks the lscbx instruction, but some
application programs that run on processors that
implement Power ISA may still use lscbx, and
privileged software may emulate the instruction.
XER48:55 may be assigned a meaning in a future
version of the architecture, when POWER compati-
bility for lscbx is no longer needed, so these bits
should not be used for purposes other than the
lscbx comparison byte.
Comment 6 Luke Kenneth Casson Leighton 2020-06-05 05:02:08 BST
TODO: MFSPR/MTSPR need fast-reg decoding in PowerDecoder2 DecodeA and DecodeOut
Comment 7 Luke Kenneth Casson Leighton 2020-07-07 12:22:11 BST
*** Bug 315 has been marked as a duplicate of this bug. ***
Comment 8 Luke Kenneth Casson Leighton 2020-08-31 11:34:20 BST
commit 67edc3c40a5aba2f2f3328225830e417d5297304 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Mon Aug 31 11:33:10 2020 +0100

    add XER to fastregs and "construct" it in mfspr/mtspr