Bug 465 - add LoadStore error and exception handling via PortInterface
Summary: add LoadStore error and exception handling via PortInterface
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
: 302 (view as bug list)
Depends on:
Blocks: 216 383
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Reported: 2020-08-18 13:56 BST by Luke Kenneth Casson Leighton
Modified: 2021-09-12 14:38 BST (History)
2 users (show)

See Also:
NLnet milestone: NLNet.2019.10.Wishbone
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Description Luke Kenneth Casson Leighton 2020-08-18 13:56:43 BST
LOAD STORE operations must generate exceptions on failures.  these need to be identified, added to PortInterface, and implemented.
Comment 1 Tobias Platen 2020-08-19 18:46:25 BST
STORE operation fill fail if one tries to write to ROM. 
Both LOAD and STORE operations will fail if the address is outside the range that can be accessed. If the MMU is enabled, dereferencing a NULL pointer will create an exception. I propose to add an enum to PortInterface that captures the possible exception reasons: 

0 for no error
1 for an invalid address
2 when attempting to write to ROM
3 page fault
.....

there is an "exception if rolls" comment in soc/src/soc/scoreboard/addr_split.py
which needs to be implemented properly. Currently this sets a single bit that is ignored.
Comment 2 Luke Kenneth Casson Leighton 2020-08-19 19:05:23 BST
yes, agreed.  what i would like to do is study what microwatt does,
what errors occur, from dcache.vhdl and loadstore.vhdl.  this will
also tell us clearly what types of exceptions need to be generated.
Comment 3 Luke Kenneth Casson Leighton 2020-10-03 18:42:13 BST
i just realised, this is going to need microwatt load-store (dcache path) error flags, but not instruction (icache) error flags because that is a totally diffwrent path.

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/mem_types.py;hb=HEAD

it's going to be the fields from this:
MMUToLoadStore1Type
Comment 4 Luke Kenneth Casson Leighton 2020-10-05 21:05:04 BST
        e_out.exception <= exception;
        e_out.alignment <= r.align_intr;
        e_out.instr_fault <= r.instr_fault;
        e_out.invalid <= m_in.invalid;
        e_out.badtree <= m_in.badtree;
        e_out.perm_error <= m_in.perm_error;
        e_out.rc_error <= m_in.rc_error;
        e_out.segment_fault <= m_in.segerr;
        if exception = '1' and r.instr_fault = '0' then
            v.dar := addr;
            if m_in.segerr = '0' and r.align_intr = '0' then
                v.dsisr := dsisr;
            end if;
        end if;
Comment 5 Luke Kenneth Casson Leighton 2020-10-06 14:00:30 BST
*** Bug 302 has been marked as a duplicate of this bug. ***
Comment 6 Luke Kenneth Casson Leighton 2020-10-06 14:04:09 BST
commit 0554b11cfc7dbbfa2022ca304b193b91b6c39c04 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Tue Oct 6 14:03:53 2020 +0100

    add LDSTException to PortInterface
Comment 7 Luke Kenneth Casson Leighton 2020-10-06 16:07:52 BST
commit 3df06e5cc2009b5918db8eee43785d1fc1f15866 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Tue Oct 6 16:07:32 2020 +0100

    add LDSTException decode/handling in PowerDecoder2
Comment 8 Luke Kenneth Casson Leighton 2020-10-06 17:00:41 BST
commit 20afbd096e75c1fa88f6ba07a5d7804b76b8a971 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Tue Oct 6 16:58:14 2020 +0100

    add SRR1 setting for LDST memory exception trap
Comment 9 Luke Kenneth Casson Leighton 2021-05-09 02:11:55 BST
the path needs much better comments, how the exception gets through to SRR1
Comment 10 Luke Kenneth Casson Leighton 2021-05-11 11:18:01 BST
slowly getting there. most of the cases now added: instruction fault,
misalign, mmu invalid/perm_error etc.