the pipeline contexts need some extra fields: exceptions, predication masks, element widths and zeroing. https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/pipe_data.py;h=a9318eb5887f5ff8ad9551375c703d22cdb2570b;hb=e2f40b45fd234e70bd69eb195e4d3fe47943993b#l68 https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/compunits/compunits.py;h=e628c0820bbe52e5f9e1aa24afe5d779748ed76d;hb=e2f40b45fd234e70bd69eb195e4d3fe47943993b#l112 PipeContext is what creates the muxid and the op, on every pipeline stage https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/concurrentunit.py;h=6d2ff3d56b814b4bf50b3890e58a5678d3160b5d;hb=fd8a872b54a5399804042fc08af7e72086a26cc7#l46 CompALUBaseOp is the base for all stage input records, this becomes PipeContext.op: https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/base_input_record.py;h=524ad073e18f6c9bffbd23d7cab75c3b82f23a22;hb=HEAD#l10 https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/compldst_multi.py;h=807d15bfb793fd5bcaf5a2bdefb0aca5a2f47537;hb=HEAD#l495 https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/pimem.py;h=1a66b914b5885d29a676bcd6ddbf67b4363bbc2f;hb=HEAD#l294
http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-May/002518.html this is quite a complex chain. links to source code to be added to first comment.
commit 5919b89de8a6f1bb7fce42c8cacd9dd38f126901 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Tue May 4 13:31:35 2021 +0100 add option to add exception type to FUBaseData (pipe_data)
commit 68fb6b858b7cabc4fbc2b7c66be409aa391c8153 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Tue May 4 13:35:54 2021 +0100 add LDSTException class to LDSTOutputData
commit 7d8165c511127319183db8763a65c87ee7e25ea7 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Tue May 4 17:02:49 2021 +0100 note a way to see if an exception happened, in TestIssuer
renamed PowerDecoder2.exc to PowerDecoder2.ldst_exc https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=fc909b841a99f27117d322f3c8ffd02f1c01cb4b the exception is given *top priority* in *re-writing* the instruction in PowerDecoder2: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_decoder2.py;h=63b0796bc258c8bed4ef800b563835c5d243b85d;hb=fc909b841a99f27117d322f3c8ffd02f1c01cb4b#l1255 (there is a list of if-elif-elif statements, there: LDST exception is top priority)
this is nowhere near sophisticated enough, and may leave some latches hi after an exception https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/pimem.py;hb=HEAD#l294
base_input_record.py CompALUBaseOp is probably the best location to auto-extend the op instance with necessary global flags such as predicate mask, zeroing options, subvl, saturation modes etc. this should really be done in a way that does not require huge manual intervention and maintenance to update: similar technique to PowerOp and PowerDecoder2.do_copy(). in fact, with do_copy() already hooking into the CompOpSubset record it is harder *not* to use do_copy().
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/alu/alu_input_record.py;hb=HEAD example, derived from CompOpSubsetBase. perhaps overthinking this. just define a list of SV layout properties that the input records need to have, and extend the input records in their constructor. makes it clear what each input record actually has.
should be as simple as this: commit 73165df2e3ed5c33248141f66c8c8f37c2a18235 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Wed May 5 12:51:26 2021 +0100 add SVP64 RM fields to ALU input record where the fields to be added are listed in power_svp64_rm.py sv_input_record_layout = [ ('sv_pred_sz', 1), # predicate source zeroing ('sv_pred_dz', 1), # predicate dest zeroing ('sv_saturate', SVP64sat), #('sv_RC1', 1), ]
decided it needed to go onto CompOpSubsetBase after all --- a/src/soc/fu/base_input_record.py +++ b/src/soc/fu/base_input_record.py @@ -1,6 +1,9 @@ from nmigen.hdl.rec import Record, Layout from nmigen import Signal +# needed for SVP64 information at the pipeline +from openpower.decoder.power_svp64_rm import sv_input_record_layout + class CompOpSubsetBase(Record): """CompOpSubsetBase @@ -15,6 +18,7 @@ class CompOpSubsetBase(Record): assert name.endswith("OpSubset") name = name[4:-8].lower() + "_op" + layout = list(layout) + sv_input_record_layout Record.__init__(self, Layout(layout), name=name) # grrr. Record does not have kwargs
this may need some additional checking, esp. for 3-operand (and RS) commit c8dbc9446617f210d06bd796c7ff5a5a026d6c87 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Wed May 5 16:33:48 2021 +0100 if zeroing is set, put zero into input or output as requested +Subproject commit 227f39952a4529cea7f5da76c361bf6b650adff3-dirty diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py index 09a02006..53e023ad 100644 --- a/src/soc/fu/common_input_stage.py +++ b/src/soc/fu/common_input_stage.py @@ -31,7 +31,9 @@ class CommonInputStage(PipeModBase): else: comb += a.eq(self.i.a) - comb += self.o.a.eq(a) + # SV zeroing on predicate source zeros the input + with m.If(~op.sv_pred_sz): + comb += self.o.a.eq(a) ##### operand B ##### @@ -46,7 +48,9 @@ class CommonInputStage(PipeModBase): else: comb += b.eq(self.i.b) - comb += self.o.b.eq(b) + # SV zeroing on predicate source zeros the input + with m.If(~op.sv_pred_sz): + comb += self.o.b.eq(b) ##### carry-in #####
(In reply to Luke Kenneth Casson Leighton from comment #11) > this may need some additional checking, esp. for 3-operand > (and RS) nope, won't work quite correctly (for dest zeroing), the CR has to be checked if the result is equal to zero.