Bug 491 - MMU POWER9 pipeline needed
Summary: MMU POWER9 pipeline needed
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on: 525
Blocks: 51 383
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Reported: 2020-09-15 00:36 BST by Luke Kenneth Casson Leighton
Modified: 2020-11-04 18:12 GMT (History)
1 user (show)

See Also:
NLnet milestone: NLnet.2019.02
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Description Luke Kenneth Casson Leighton 2020-09-15 00:36:17 BST
some opcodes such as tlbie and dcbz as well as those setting pte all really need tobe in their own pipeline.
Comment 1 Luke Kenneth Casson Leighton 2020-09-15 10:56:28 BST
decision here, anything to do with tlbie, or dcbz and cache or mmu in general goes into this Function Unit.

means creating a new FU in the CSV files (adding to power_enums.py)

it will need to be a FSM not a pipeline because it gets too complex otherwise.

changing tlbie etc not expected to be particularly common so this is ok.
Comment 2 Luke Kenneth Casson Leighton 2020-09-16 01:48:36 BST
 -- send MMU-related SPRs to loadstore1
    case sprn is
             v.decode.unit := LDST;

in PowerDecoder2 must redirect these SPRs to the MMU FU
Comment 3 Luke Kenneth Casson Leighton 2020-09-16 01:51:20 BST
        majorop := unsigned(f_in.insn(31 downto 26));
        if f_in.fetch_failed = '1' then
            v.valid := '1';
            -- Only send down a single OP_FETCH_FAILED
            if r.decode.insn_type = OP_FETCH_FAILED then
                v.valid := '0';
            end if;
            v.decode := fetch_fail_inst;

also, like interrupts, if a fetch fails run a new op (microcode style)