Bug 525 - add dcbz pseudocode
Summary: add dcbz pseudocode
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on:
Blocks: 383 450 491
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Reported: 2020-11-04 18:10 GMT by Luke Kenneth Casson Leighton
Modified: 2020-11-05 11:26 GMT (History)
1 user (show)

See Also:
NLnet milestone: NLNet.2019.10.043.Wishbone
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Description Luke Kenneth Casson Leighton 2020-11-04 18:10:48 GMT
the following pseudocode adapted from p850 v3.0B needs to be added to the
openpower isa pages git.libre-soc.org, probably fixedstore.mdwn for now

# Data Cache Block set to Zero


* dcbz RA,RB


    if RA = 0 then b <= 0
    else           b <- (RA)
    EA <- b + (RB)
    n <- block size (bytes)
    m <- log2(n)
    ea <- EA[0:63-m] || [0]*m
    m8 <- m*8
    MEM(ea, n) <- [0]*m8

Special Registers Altered:


a rebuild using pywriter (see top-level Makefile) is required after adding
the pseudocode.
Comment 1 Luke Kenneth Casson Leighton 2020-11-04 19:23:12 GMT
i took a look at this and i can't work out what the pseudocode is actually
supposed to do.  i've asked on openhdl-cores for advice.
Comment 2 Luke Kenneth Casson Leighton 2020-11-05 11:26:56 GMT
heard from Ben and Paul, *we* choose the block size (sigh).