Bug 637 - add SVSRR0 to TRAP pipeline
Summary: add SVSRR0 to TRAP pipeline
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on:
Reported: 2021-05-04 18:06 BST by Luke Kenneth Casson Leighton
Modified: 2021-05-04 18:41 BST (History)
1 user (show)

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Description Luke Kenneth Casson Leighton 2021-05-04 18:06:40 BST
SVSRR0 needs to be added to the trap pipeline, similar to SRR0 and SRR1
recording SVSTATE.
Comment 1 Luke Kenneth Casson Leighton 2021-05-04 18:41:14 BST
commit 321afe236aa1e44a99a94a774c3e6b412a61e8d9 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Tue May 4 18:40:35 2021 +0100

    add SVSTATE (SVSRR0) to TRAP pipeline
    involves adding svstate to TrapOutputData regspec, and a corresponding
    write port to StateRegs, and adding svstate to CompTrapOpSubset