we need a management / low-power-mode / boot-up core may also be used for bit-banging of I/O, to create buses not envisioned during the initial processor design.
https://github.com/lambdaconcept/minerva http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu&type=tree
using XIP from QSPI instead