Once #517 JTAG STLINKv2 to FPGA connection guide wiki is complete:
* lckl to outline Libre-SOC test chip boot via jtag procedure for testing on FPGA before the test ASIC is taped-out
*cole to make the wiki page and help with refining the JTAG process until lkcl is satisfied that it is totally correct
*note* lkcl I set the due date to two weeks from the creation of this bug report because it needs to be tested prior to the ASIC being taped out, which I believe is sometime in march, please adjust the due date as you see fit
ecp5_fpga wiki url: https://libre-soc.org/HDL_workflow/ECP5_FPGA/
Precursor bug report currently in its final stages: https://bugs.libre-soc.org/show_bug.cgi?id=517
Bug #517 covers the creation and the wiki page that provides instructions on the the setup of STLINKv2 to FPGA wiring, ensuring their correctness so when connected to power and used as as specified, the devices do not blow up and release all the magic computer smoke they require to function.
SOC JTAG testing steps(?):
* Put processor into HALT
* Upload binary to address 0xXXXX via STLINKv2
(In reply to Cole Poirier from comment #0)
> Once #517 JTAG STLINKv2 to FPGA connection guide wiki is complete:
> * lkcl to outline Libre-SOC test chip boot via jtag procedure for testing on
> FPGA before the test ASIC is taped-out
in the README is the version for sim.py
the FPGA and ASIC variant is near-identical.
also this can be run (it uploads bytes 0x1 and 0x2 presently, needs to be given a filename)
it can be used to talk jtagremote protocol (via openocd) so that it actually
connects directly to the FPGA (or ASIC) and uploads firmware to it.